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AD8158 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8158
Beschreibung 6.5 Gbps Quad Buffer Mux/Demux
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD8158 Datasheet, Funktion
FEATURES
Quad 2:1 mux/1:2 demux
Optimized for dc to 6.5 Gbps NRZ data
Per-lane P/N pair inversion for routing ease
Programmable input equalization
Compensates up to 40 inches of FR4
Loss-of-signal detection
Programmable output pre-emphasis up to 12 dB
Programmable output levels with squelch and disable
Accepts ac-coupled or dc-coupled differential CML inputs
50 Ω on-chip termination
1:2 demux supports unicast or bicast operation
Port-level loopback
Port or single lane switching
1.8 V to 3.3 V flexible core supply
User-settable I/O supply from VCC to 1.2 V
Low power, typically 2.0 W in basic configuration
100-lead LFCSP
−40°C to +85°C operating temperature range
APPLICATIONS
Low cost redundancy switch
SONET OC48/SDH16 and lower data rates
XAUI/GbE/FC/Infiniband over backplane
OIF CEI 6.25 Gbps over backplane
Serial data-level shift
4-/8-/12-lane equalizers or redrivers
GENERAL DESCRIPTION
The AD8158 is an asynchronous, protocol-agnostic, quad-lane
2:1 switch with a total of 12 differential CML inputs and
12 differential CML outputs. The signal path supports NRZ
signaling with data rates up to 6.5 Gbps per lane. Each lane
offers programmable receive equalization, programmable
output pre-emphasis, programmable output levels, and loss-of-
signal detection.
The nonblocking switch-core of the AD8158 implements a
2:1 multiplexer and 1:2 demultiplexer per lane and supports
independent lane switching through the four select pins,
SEL[3:0]. Each port is a four-lane link. Every lane implements
an asynchronous path supporting dc to 6.5 Gbps NRZ data,
fully independent of other lanes. The AD8158 has low latency
and very low lane-to-lane skew.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
6.5 Gbps
Quad Buffer Mux/Demux
AD8158
Ix_A[3:0]
Ix_B[3:0]
FUNCTIONAL BLOCK DIAGRAM
RECEIVE
EQUALIZATION
EQ
EQ
2:1
TRANSMIT
PRE-
EMPHASIS
Ox_C[3:0]
Ox_A[3:0]
Ox_B[3:0]
SCL
SDA
I2C_A0
I2C_A1
I2C_A2
TRANSMIT
PRE-
EMPHASIS
I2C
CONTROL
LOGIC
AD8158
1:2 EQ Ix_C[3:0]
QUAD
2:1
MULTIPLEXER/
1:2
DEMULTIPLEXER
RECEIVE
EQUALIZATION
TOGGLE
CONTROL
LOGIC
LB_A
LB_B
LB_C
PE_A
PE_B
PE_C
EQ_A[1:0]
EQ_B[1:0]
EQ_C[1:0]
SEL[3:0]
BICAST
SEL4G
RESETb
LOS_INT
Figure 1.
The main application of the AD8158 is to support redundancy
on both the backplane and the line interface sides of a serial
link. The demultiplexing path implements unicast and bicast
capability, allowing the part to support either 1 + 1 or 1:1
redundancy.
The AD8158 is also suited for testing high speed serial links
because of its ability to duplicate incoming data. In a port-
monitoring application, the AD8158 can maintain link-
connectivity with a pass-through connection from Port C to
Port A while sending a duplicate copy of the data to test
equipment on Port B.
The rich feature set of the AD8158 can be controlled either
through external toggle pins or by setting on-chip control
registers through the I2C interface.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.






AD8158 Datasheet, Funktion
AD8158
I2C TIMING SPECIFICATIONS
SDA
tF
tLOW
tR tSU;DAT
tF
tHD;STA
tR tBUF
SCL
tHD;STA
S
NOTES
1. S = START CONDITION.
2. Sr = REPEAT START.
3. P = STOP.
tHD;DAT
tHIGH
tSU;STA
Sr
Figure 2. I2C Timing Diagram
tSU;STO
P
S
Table 2. I2C Timing Parameters
Parameter
SCL Clock Frequency
Hold Time for a Start Condition
Setup Time for a Repeated Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Data Hold Time
Data Setup Time
Rise Time for Both SDA and SCL
Fall Time for Both SDA and SCL
Setup Time for Stop Condition
Bus Free Time Between a Stop and a Start Condition
Bus Free Time After a Reset
Reset Pulse Width1
Symbol
fSCL
tHD;STA
tSU;STA
tLOW
tHIGH
tHD;DAT
tSU;DAT
tR
tF
tSU;STO
tBUF
Min Max
0 400+
0.6
0.6
1.3
0.6
0
10
1 300
1 300
0.6
1
1
10
Unit
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
μs
ns
1 Reset pulse width is defined as the time RESETB is held below the logic low threshold (VIL) listed in Table 1 while the DVCC supply is within the operating range in Table 1.
Rev. B | Page 5 of 36

6 Page









AD8158 pdf, datenblatt
AD8158
50CABLES
50CABLES
50CABLES
DATA OUT 2
2 FR4 TEST BACKPLANE 2
2 INPUT OUTPUT 2
PIN PIN
2
50
PATTERN
GENERATOR
DIFFERENTIAL
TP1 STRIPLINE TRACES
8mils WIDE, 8mils SPACE,
8mils DIELECTRIC HEIGHT
AD8158
TP2 AC-COUPLED
EVALUATION
BOARD
HIGH
TP3 SPEED
SAMPLING
OSCILLOSCOPE
TRACE LENGTHS = 20 INCHES,
40 INCHES
25ps/DIV
REFERENCE EYE DIAGRAM AT TP1
Figure 7. Input Equalization Test Circuit
25ps/DIV
Figure 8. 6.5 Gbps Input Eye, 20 Inch FR4 Input Channel (TP2 from Figure 7)
25ps/DIV
Figure 10. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel (TP3 from Figure 7)
25ps/DIV
Figure 9. 6.5 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 7)
25ps/DIV
Figure 11. 6.5 Gbps Output Eye, 40 Inch FR4 Input Channel (TP3 from Figure 7)
Rev. B | Page 11 of 36

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