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PDF AD7091R-2 Data sheet ( Hoja de datos )
| Número de pieza | AD7091R-2 | |
| Descripción | 12-Bit SAR ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
2-/4-/8-Channel, 1 MSPS,
Ultralow Power, 12-Bit SAR ADC
AD7091R-2/AD7091R-4/AD7091R-8
FEATURES
Ultralow system power
Flexible power/throughput rate management
Normal mode
1.4 mW at 1 MSPS
Power-down mode
550 nA typical at VDD = 5.25 V
435 nA typical at VDD = 3 V
Programmable ALERT interrupt pin (4-/8-channel models)
High performance
1 MSPS throughput with no latency/pipeline delay
SNR: 70 dB typical at 10 kHz input frequency
THD: −80 dB typical at 10 kHz input frequency
INL: ±0.7 LSB typical, ±1.0 LSB maximum
Small system footprint
On-chip accurate 2.5 V reference, 5 ppm/°C typical drift
MUXOUT/ADCIN to allow single buffer amplifier
Daisy-chain mode
16-lead, 20-lead, and 24-lead 4 mm × 4 mm LFCSP packages
16-lead, 20-lead, and 24-lead TSSOP packages
Easy to use
SPI/QSPI™/MICROWIRE™/DSP compatible digital interface
Integrated programmable channel sequencer
BUSY indication available (4-/8-channel models)
Built in features for control and monitoring applications
GPOx pins available (4-/8-channel models)
Wide operating range
Temperature range: −40°C to +125°C
Specified for VDD of 2.7 V to 5.25 V
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
Optical sensors
Diagnostic/monitoring functions
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
MUXOUT ADCIN VDD
REFIN/
REFOUT
REGCAP
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
I/P
MUX
CHANNEL
SEQUENCER
2.5V
VREF
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
ON-CHIP
OSC
CONTROL LOGIC
AND REGISTERS
AD7091R-8
VDRIVE
RESET
CONVST
SDO
SDI
SCLK
CS
GND
Figure 1.
ALERT/
BUSY/
GPO0
GPO1
GND
GENERAL DESCRIPTION
The AD7091R-2/AD7091R-4/AD7091R-8 family is a multichannel
12-bit, ultralow power, successive approximation analog-to-
digital converter (ADC) that is available in two, four, or eight
analog input channel options. The AD7091R-2/AD7091R-4/
AD7091R-8 operate from a single 2.7 V to 5.25 V power supply
and are capable of achieving a sampling rate of 1 MSPS.
The AD7091R-2/AD7091R-4/AD7091R-8 family offers up to eight
single-ended analog input channels with a channel sequencer
that allows a preprogrammed selection of channels to be converted
sequentially. The AD7091R-2/AD7091R-4/ AD7091R-8 also
feature an on-chip conversion clock, an on-chip accurate 2.5 V
reference, and a high speed serial interface.
The AD7091R-2/AD7091R-4/AD7091R-8 have a serial port
interface (SPI) that allows data to be read after the conversion
while achieving a 1 MSPS throughput rate. The conversion process
and data acquisition are controlled using the CONVST pin.
The AD7091R-2/AD7091R-4/AD7091R-8 use advanced design
techniques to achieve ultralow power dissipation at high
throughput rates. They also feature flexible power management
options. An on-chip configuration register allows the user to set up
different operating conditions. These include power management,
alert functionality, busy indication, channel sequencing, and
general-purpose output pins. The MUXOUT and ADCIN pins
allow signal conditioning of the multiplexer output prior to
acquisition by the ADC.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 1.8 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Conversion Time: CONVST Falling Edge to Data Available
Acquisition Time
Time Between Conversions (Normal Mode)
CONVST Pulse Width
SCLK Period (Normal Mode)
VDRIVE Above 2.7 V
VDRIVE Above 1.8 V
SCLK Period (Chain Mode)
VDRIVE Above 2.7 V
VDRIVE Above 1.8 V
SCLK Low Time
SCLK High Time
SCLK Falling Edge to Data Remains Valid
SCLK Falling Edge to Data Valid Delay
VDRIVE Above 4.5 V
VDRIVE Above 3.3 V
VDRIVE Above 2.7 V
VDRIVE Above 1.8 V
End of Conversion to CS Falling Edge
CS Low to SDO Enabled
CS High or Last SCLK Falling Edge to SDO High Impedance
SDI Data Setup Time Prior to SCLK Rising Edge
SDI Data Hold Time After SCLK Rising Edge
Last SCLK Falling Edge to Next CONVST Falling Edge
RESET Pulse Width
RESET Pulse Delay Upon Power Up
Time Between Conversions (Power On Software Reset)
Symbol
tCONVERT
tACQ
tCYC
tCNVPW
tSCLK
tSCLK
tSCLKL
tSCLKH
tHSDO
tDSDO
Min
400
1000
10
16
22
20
25
6
6
5
tEOCCSL
tEN
tDIS
tSSDISCLK
tHSDISCLK
tQUIET
tRESETPW
tRESET_DELAY
tCYC_RESET
5
5
2
50
10
50
2
Typ Max
600
500
12
13
14
20
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
500µA
IOL
TO SDO
20pCFL
500µA
IOH
1.4V
Figure 2. Load Circuit for Digital Interface Timing
X% VDRIVE
Y% VDRIVE
tDELAY
tDELAY
VIH2
VIL2
VIH2
VIL2
NOTES
12FMOINRIMVUDRMIVVEIH≤
3.0V, X = 90 AND Y
AND MAXIMUM VIL
= 10; FOR VDRIVE > 3.0V, X = 70 AND Y = 30.
USED. SEE SPECIFICATIONS FOR DIGITAL
INPUTS PARAMETER IN TABLE 2.
Figure 3. Voltage Levels for Timing
Rev. C | Page 5 of 42
5 Page 
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
CS 1
24 VDRIVE
RESET 2
23 CONVST
VDD 3
REGCAP 4
22 SCLK
21 SDO
REFIN/REFOUT 5
20 SDI
GND 6 AD7091R-8 19 GND
TOP VIEW
MUXOUT 7 (Not to Scale) 18 ADCIN
VIN0 8
17 VIN1
VIN2 9
16 VIN3
ALERT/BUSY/GPO0 10
VIN4 11
VIN6 12
15 GPO1
14 VIN5
13 VIN7
Figure 9. 8-Channel, 24-Lead TSSOP Pin Configuration
VDD 1
REGCAP 2
REFIN/REFOUT 3
GND 4
MUXOUT 5
VIN0 6
AD7091R-8
TOP VIEW
(Not to Scale)
18 SDI
17 GND
16 ADCIN
15 VIN1
14 VIN3
13 GPO1
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. IT IS RECOMMENDED THAT
THE PAD BE SOLDERED TO GND.
Figure 10. 8-Channel, 24-Lead LFCSP Pin Configuration
Table 7. 8-Channel, 24-Lead LFCSP and 24-Lead TSSOP Pin Function Descriptions
Pin No.
TSSOP
LFCSP Mnemonic
Description
1 23 CS
Chip Select Input. When CS is held low, the serial bus enables, and CS frames the output data
on the SPI.
2 24 RESET
Reset. Logic input.
3 1 VDD
4 2 REGCAP
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this output pin
separately to GND using a 1.0 μF capacitor.
5 3 REFIN/REFOUT
6, 19 4, 17 GND
Voltage Reference Output, 2.5 V. Decouple this pin to GND. Typical recommended decoupling
capacitor value is 2.2 μF. The user can either access the internal 2.5 V reference or overdrive the
internal reference with the voltage applied to this pin. The reference voltage range for an
externally applied reference is 1.0 V to VDD.
Chip Ground Pins. These pins are the ground reference point for all circuitry on the AD7091R-8.
7 5 MUXOUT
8 6 VIN0
Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or
buffering is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the
conditioning network to the ADCIN pin.
Analog Input 0. Single-ended analog input. The analog input range is 0 V to VREF.
9 7 VIN2
Analog Input 2. Single-ended analog input. The analog input range is 0 V to VREF.
10 8 ALERT/BUSY/GPO0 Alert Output Pin (ALERT). This is a multifunction pin determined by the configuration register.
When functioning as ALERT, this pin is a logic output indicating that a conversion result has
fallen outside the limit of the register settings.
When the ALERT/BUSY/GPO0 pin is configured as a BUSY output, use this pin to indicate when a
conversion is taking place.
The pin can also function as a general-purpose digital output.
11 9 VIN4
12 10 VIN6
13 11 VIN7
14 12 VIN5
Analog Input 4. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 6. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 7. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 5. Single-ended analog input. The analog input range is 0 V to VREF.
15 13 GPO1
General-Purpose Digital Output.
16 14 VIN3
Analog Input 3. Single-ended analog input. The analog input range is 0 V to VREF.
17 15 VIN1
18 16 ADCIN
Analog Input 1. Single-ended analog input. The analog input range is 0 V to VREF.
ADC Input. This pin allows access to the on-chip track-and-hold. If no external filtering or
buffering is required, tie this pin directly to the MUXOUT pin; otherwise, tie the input of the
conditioning network to the MUXOUT pin.
Rev. C | Page 11 of 42
11 Page | ||
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| PDF Descargar | [ Datasheet AD7091R-2.PDF ] | |
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