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AD7988-5 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7988-5
Beschreibung 16-Bit Lower Power PulSAR ADCs
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 23 Seiten
AD7988-5 Datasheet, Funktion
Data Sheet
16-Bit Lower Power
PulSAR ADCs in MSOP/LFCSP
AD7988-1/AD7988-5
FEATURES
Low power dissipation
AD7988-1
400 µW at 100 kSPS (VDD only)
700 µW at 100 kSPS (total)
AD7988-5
2 mW at 500 kSPS (VDD only)
3.5 mW at 500 kSPS (total)
16-bit resolution with no missing codes
Throughput: 100 kSPS/500 kSPS options
INL: ±0.6 LSB typical, ±1.25 LSB maximum
SINAD: 91.5 dB at 10 kHz
THD: −114 dB at 10 kHz
Pseudo differential analog input range
0 V to VREF with VREF from 2.5 V to 5.5 V
No pipeline delay
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic
interface
Proprietary SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
serial interface
Daisy-chain multiple ADCs
10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP, same space
as SOT-23
Wide operating temperature range: −40°C to +125°C
APPLICATIONS
Battery-powered equipment
Low power data acquisition systems
Portable medical instruments
ATE equipment
Data acquisitions
Communications
GENERAL DESCRIPTION
The AD7988-1/AD7988-51 are 16-bit, successive approximation,
analog-to-digital converters (ADC) that operate from a single
power supply, VDD. The AD7988-1 offers a 100 kSPS throughput,
and the AD7988-5 offers a 500 kSPS throughput. They are low
power, 16-bit sampling ADCs with a versatile serial interface
port. On the CNV rising edge, they sample an analog input,
IN+, between 0 V to VREF with respect to a ground sense, IN−.
The reference voltage, REF, is applied externally and can be set
independent of the supply voltage, VDD.
The SPI-compatible serial interface also features the ability to
daisy-chain several ADCs on a single 3-wire bus using the SDI
input. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using
the separate supply, VIO.
The AD7988-1/AD7988-5 generics are housed in a 10-lead
MSOP or a 10-lead LFCSP with operation specified from −40°C
to +125°C.
Table 1. MSOP, LFCSP 14-/16-/18-Bit PulSAR® ADCs
Bits 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS
181 AD7989-12 AD76912 AD76902
AD79822
AD7989-52
AD79842
161 AD7684
AD76872 AD76882
AD79152
AD76932
AD79162
163 AD7680
AD76852 AD76862
AD79802
AD7683
AD7694
AD7988-52
AD79832
AD7988-12
143 AD7940
AD79422 AD79462
1 True differential.
2 Pin-for-pin compatible.
3 Pseudo differential.
TYPICAL APPLICATION CIRCUIT
2.5V TO 5V 2.5V
0V TO VREF
REF VDD VIO
IN+ AD7988-1/ SDI
IN–
AD7988-5
SCK
SDO
GND
CNV
Figure 1.
1.8V TO 5.5V
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
1 Protected by U.S. Patent 6,703,961.
Rev. F
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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AD7988-5 Datasheet, Funktion
AD7988-1/AD7988-5
Data Sheet
VDD = 2.37 V to 2.63 V, VIO = 1.71 V to 3.3 V, −40°C to +125°C unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 5.
Parameter
AD7988-1
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
AD7988-5
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
B Grade
C Grade
Acquisition Time
B Grade
C Grade
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
Symbol Min
tCONV
tACQ
tCYC
500
10
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
400
800
2
500
22
23
6
6
3
5
10
0
5
5
2
3
Typ Max Unit
100 kHz
9.5 μs
ns
μs
500 kHz
1.6 μs
1.2 μs
14 21
18 40
20
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
500µA IOL
TO SDO
CL
20pF
1.4V
500µA IOH
Figure 2. Load Circuit for Digital Interface Timing
X% VIO1
tDELAY
VIH2
VIL2
Y% VIO1
tDELAY
VIH2
VIL2
1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
Figure 3. Voltage Levels for Timing
Rev. F | Page 6 of 23

6 Page









AD7988-5 pdf, datenblatt
AD7988-1/AD7988-5
95
94
93
92
91
90
89
88
87
86
85
–10 –9
–8 –7 –6 –5 –4 –3 –2
INPUT LEVEL (dB OF FULL SCALE)
Figure 18. SNR vs. Input Level
–1
0
–95 115
–100
SFDR
110
–105
105
–110
100
–115
THD
95
–120
90
–125
2.25
2.75 3.25 3.75 4.25 4.75
REFERENCE VOLTAGE (V)
Figure 19. THD, SFDR vs. Reference Voltage
85
5.25
100
95
90
85
80
10
100
FREQUENCY (kHz)
Figure 20. SINAD vs. Frequency
1k
Data Sheet
95
93
91
89
87
85
–55 –35 –15
5
25 45 65 85
TEMPERATURE (°C)
Figure 21. SNR vs. Temperature
105 125
0.7
IVDD
0.6
0.5
0.4
0.3
0.2
0.1
0
2.375
2.425
IREF
IVIO
2.475
2.525
VDD VOLTAGE (V)
2.575
2.625
Figure 22. Operating Currents vs. Supply (AD7988-5)
0.14
0.12
IVDD
0.10
0.08
0.06
0.04
0.02
IREF
IVIO
0
2.375
2.425
2.475
2.525
2.575
2.625
VDD VOLTAGE (V)
Figure 23. Operating Currents vs. Supply (AD7988-1)
Rev. F | Page 12 of 23

12 Page





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