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AD7923 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7923
Beschreibung 200 kSPS 12-Bit ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
AD7923 Datasheet, Funktion
Data Sheet
4-Channel, 200 kSPS 12-Bit ADC
with Sequencer in 16-Lead TSSOP
AD7923
FEATURES
Fast throughput rate: 200 kSPS
Specified for AVDD of 2.7 V to 5.25 V
Low power
3.6 mW max at 200 kSPS with 3 V supply
7.5 mW max at 200 kSPS with 5 V supply
4 (single-ended) inputs with sequencer
Wide input bandwidth
70 dB Min SNR at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface SPI®-/QSPITM-/
MICROWIRETM-/DSP-compatible
Shutdown mode: 0.5 μA max
16-lead TSSOP package
Qualified for automotive applications
GENERAL DESCRIPTION
The AD7923 is a 12-bit, high speed, low power, 4-channel, suc-
cessive approximation (SAR) ADC. It operates from a single
2.7 V to 5.25 V power supply and features throughput rates up to
200 kSPS. It contains a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 8 MHz.
The conversion process and data acquisition are controlled by
CS and the serial clock, allowing the device to easily interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS; the conversion is also initiated at this
point.
The AD7923 uses advanced design techniques to achieve very
low power dissipation at maximum throughput rates. At
maximum throughput rates, it consumes 1.2 mA maximum
with 3 V supplies and 1.5 mA maximum with 5 V supplies.
Through the configuration of the control register, the analog
input range can be selected as 0 V to REFIN or 0 V to 2 × REFIN,
with either straight binary or twos complement output coding.
The AD7923 features four single-ended analog inputs with a
channel sequencer to allow a preprogrammed selection of
channels to be converted sequentially.
The conversion time for the AD7923 is determined by the serial
clock, SCLK, frequency, since this is used as the master clock to
control the conversion. The conversion time can be as short as
800 ns with a 20 MHz SCLK.
FUNCTIONAL BLOCK DIAGRAM
AVDD
REFIN
VIN0
VIN3
T/H
I/P
MUX
SEQUENCER
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL LOGIC
AD7923
GND
SCLK
DOUT
DIN
CS
VDRIVE
Figure 1.
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption.
The AD7923 offers up to 200 kSPS throughput rates. At the
maximum throughput rate with 3 V supplies, the AD7923
dissipates just 3.6 mW of power.
2. Four Single-Ended Inputs with a Channel Sequencer.
3. Single-Supply Operation with VDRIVE Function.
The VDRIVE function allows the serial interface to connect
directly to either 3 V or 5 V processor systems independent
of AVDD.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through the
serial clock speed increase. The part also features various
shutdown modes to maximize power efficiency at lower
throughput rates. Current consumption is 0.5 μA
maximum when in full shutdown.
5. No Pipeline Delay.
The part features a SAR ADC with accurate control of the
sampling instant via a CS input and once off conversion
control.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2002–2013 Analog Devices, Inc. All rights reserved.
Technical Support
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AD7923 Datasheet, Funktion
Data Sheet
AD7923
TIMING SPECIFICATIONS
AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter
fSCLK2
tCONVERT
tQUIET
AVDD = 3 V
10
20
16 × tSCLK
50
Limit at TMIN, TMAX
AVDD = 5 V Unit
10 kHz min
20 MHz max
16 × tSCLK
50 ns min
t2 10
10 ns min
t33 35
30 ns max
t43 40
40 ns max
t5
0.4 × tSCLK
0.4 × tSCLK
ns min
t6
0.4 × tSCLK
0.4 × tSCLK
ns min
t7 10
10 ns min
t8 4
15/45
15/35
ns min/max
t9 10
10 ns min
t10 5
5 ns min
t11 20
20 ns min
t12 1
1 µs max
Description
Minimum quiet time required between CS rising edge and start of next
conversion
CS to SCLK set-up time
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
SCLK falling edge to DOUT high impedance
DIN set-up time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Sixteenth SCLK falling edge to CS high
Power-Up time from full power-down/auto shutdown mode
1 Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 2.
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2 The mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t8, is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
IOL
TO OUTPUT
PIN CL
50pF
200µA
IOH
1.6V
Figure 2. Load Circuit for Digital Output Timing Specification
Rev. D | Page 5 of 24

6 Page









AD7923 pdf, datenblatt
Data Sheet
Signal-to-(Noise + Distortion) (SINAD) Ratio
This is the measured ratio of SINAD at the output of the ADC.
The signal is the rms amplitude of the fundamental. Noise is the
sum of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc. The ratio is dependent on the
number of quantization levels in the digitization process, the
more levels, the smaller the quantization noise. The theoretical
SINAD ratio for an ideal N-bit converter with a sine wave input
is given by
SINAD = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
AD7923
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7923, it is defined as
THD(dB) = 20 log
V22 + V32 + V42 + V52 + V62
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Rev. D | Page 11 of 24

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