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PDF AD7910 Data sheet ( Hoja de datos )
| Número de pieza | AD7910 | |
| Descripción | 10-/12-Bit ADCs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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250 kSPS,
10-/12-Bit ADCs in 6-Lead SC70
AD7910/AD7920
FEATURES
Throughput rate: 250 kSPS
Specified for VDD of 2.35 V to 5.25 V
Low power
3.6 mW typ at 250 kSPS with 3 V supplies
12.5 mW typ at 250 kSPS with 5 V supplies
Wide input bandwidth
71 dB SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Standby mode: 1 μA max
6-lead SC70 package
8-lead MSOP package
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors
GENERAL DESCRIPTION
The AD7910/AD79201 are, respectively, 10-bit and 12-bit, high
speed, low power, successive approximation ADCs. The parts
operate from a single 2.35 V to 5.25 V power supply and feature
throughput rates up to 250 kSPS. The parts contain a low noise,
wide bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 13 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is initiated at this
point. There are no pipeline delays associated with the part.
The AD7910/AD7920 use advanced design techniques to
achieve very low power dissipation at high throughput rates.
The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 to VDD. The conversion rate
is determined by the SCLK.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN T/H
10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL LOGIC
AD7910/AD7920
GND
Figure 1.
SCLK
SDATA
CS
PRODUCT HIGHLIGHTS
1. 10-/12-bit ADCs in SC70 and MSOP packages.
2. Low power consumption.
3. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced when power-down mode is used while not
converting. The part also features a power-down mode to
maximize power efficiency at lower throughput rates.
Current consumption is 1 μA maximum and 50 nA typically
when in power-down mode.
4. Reference derived from the power supply.
5. No pipeline delay. The parts feature a standard successive
approximation ADC with accurate control of the sampling
instant via a CS input and once-off conversion control.
1 Protected by U.S. Patent No. 6,681,332.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
1 page  
AD7910/AD7920
Parameter1
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN, SCLK Pin
Input Current, IIN, CS Pin
Input Capacitance, CIN6
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance6
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time3
Throughput Rate
POWER REQUIREMENTS
VDD
IDD
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation7
Normal Mode (Operational)
Full Power-Down
A Grade 1, 2 B Grade1, 2
2.4 2.4
1.8 1.8
0.8 0.8
0.4 0.4
±0.5 ±0.5
±10 ±10
55
VDD − 0.2
VDD − 0.2
0.4 0.4
±1 ±1
55
Straight (natural) binary
3.2 3.2
250 250
250 250
2.35/5.25
2.35/5.25
2.5 2.5
1.2 1.2
33
1.4 1.4
11
15 15
4.2 4.2
55
33
1 Temperature range from −40°C to +85°C.
2 Operational from VDD = 2.0 V, with input low voltage (VINL) 0.35 V max.
3 See the Terminology section.
4 B Grade, maximum specifications apply as typical figures when VDD = 4.75 V to 5.25 V.
5 SC70 values guaranteed by characterization.
6 Guaranteed by characterization.
7 See the Power vs. Throughput Rate section.
Unit
V min
V min
V max
V max
μA max
nA typ
pF max
V min
V max
μA max
pF max
Test Conditions/Comments
VDD = 2.35 V
VDD = 3.6 V to 5.25 V
VDD = 2.35 V to 3.6 V
Typically 10 nA, VIN = 0 V or VDD
ISOURCE = 200 μA, VDD = 2.35 V to 5.25 V
ISINK = 200 μA
μs max
ns max
kSPS max
16 SCLK cycles with SCLK at 5 MHz
See the Serial Interface section
V min/max
mA typ
mA typ
mA max
mA max
μA max
Digital I/Ps = 0 V or VDD
VDD = 4.75 V to 5.25 V, SCLK on or off
VDD = 2.35 V to 3.6 V, SCLK on or off
VDD = 4.75 V to 5.25 V, fSAMPLE = 250 kSPS
VDD = 2.35 V to 3.6 V, fSAMPLE = 250 kSPS
Typically 50 nA
mW max
mW max
μW max
μW max
VDD = 5 V, fSAMPLE = 250 kSPS
VDD = 3 V, fSAMPLE = 250 kSPS
VDD = 5 V
VDD = 3 V
Rev. C | Page 5 of 24
5 Page 
1.0
VDD = 2.35V
0.8 TEMP = 25°C
fSAMPLE = 250kSPS
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
Figure 11. AD7920 DNL Performance
–10
VDD = 3.6V
–20
–30
–40
RIN = 10kΩ
–50
–60
–70 RIN = 1kΩ
–80
RIN = 130Ω
RIN = 13Ω
–90
10
RIN = 0Ω
100
INPUT FREQUENCY (kHz)
1000
Figure 12. THD vs. Analog Input Frequency for Various Source Impedances
AD7910/AD7920
–65
–70
–75
VDD = 2.35V
–80
VDD = 4.75V
–85
–90
10
VDD = 5.25V
VDD = 3.6V
VDD = 2.7V
100
INPUT FREQUENCY (kHz)
1000
Figure 13. THD vs. Analog Input Frequency for Various Supply Voltages
Rev. C | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD7910.PDF ] | |
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