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PDF AD9265 Data sheet ( Hoja de datos )

Número de pieza AD9265
Descripción 1.8V Analog-to-Digital Converter
Fabricantes Analog Devices 
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Data Sheet
16-Bit, 125 MSPS/105 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
AD9265
FEATURES
PRODUCT HIGHLIGHTS
SNR = 79.0 dBFS at 70 MHz and 125 MSPS
SFDR = 93 dBc at 70 MHz and 125 MSPS
Low power: 373 mW at 125 MSPS
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
−154.3 dBm/Hz small signal input noise with 200 Ω input
impedance at 70 MHz and 125 MSPS
Optional on-chip dither
Programmable internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
1. On-chip dither option for improved SFDR performance
with low power analog input.
2. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
3. Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
4. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock duty cycle stabilizer, DCS, power-down, test
modes, and voltage reference mode.
5. Pin compatibility with the AD9255, allowing a simple
migration from 16 bits down to 14 bits.
APPLICATIONS
Communications
Multimode digital receivers (3G)
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX,
and TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
FUNCTIONAL BLOCK DIAGRAM
SENSE RBIAS PDWN
AGND AVDD (1.8V)
LVDS LVDS_RS
VREF
VCM
VIN+
VIN–
DITHER
CLK+
CLK–
SYNC
REFERENCE
AD9265
TRACK-AND-HOLD
CLOCK
MANAGEMENT
ADC
16-BIT
16
CORE
OUTPUT
STAGING 16
CMOS OR
LVDS
(DDR)
SERIAL PORT
SVDD SCLK/ SDIO/ CSB
DFS DCS
Figure 1.
DRVDD (1.8V)
D15 TO D0
OR
DCO
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 page




AD9265 pdf
AD9265
Data Sheet
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation at 1.0 mA
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance3
Input Common-Mode Voltage
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
SVDD
Supply Current
IAVDD2
IDRVDD2
1.8 V CMOS
1.8 V LVDS
POWER CONSUMPTION
DC Input
Sine Wave Input2
DRVDD = 1.8 V
CMOS Output Mode
LVDS Output Mode
Standby Power4
Power-Down Power
Temp
Full
AD9265BCPZ-801
Min Typ Max
16
AD9265BCPZ-1051
Min Typ Max
16
AD9265BCPZ-1251
Min Typ Max
16
Unit
Bits
Full
Full
Full
Full
25°C
Full
25°C
Guaranteed
±0.05 ±0.25
±0.2 ±2.5
−1.0 +1.25
±0.6
±2.5
±1.5
Guaranteed
±0.05 ±0.25
±0.2 ±2.5
−1.0 +1.25
±0.65
±3.5
±2.0
Guaranteed
±0.05 ±0.25
±0.4 ±2.5
−1.0 +1.25
±0.7
±4.5
±3.0
% FSR
% FSR
LSB
LSB
LSB
LSB
Full ±2
Full ±15
±2
±15
±2 ppm/°C
±15 ppm/°C
Full
+8 ±12
+8 ±12
+8 ±12 mV
Full 3
3
3 mV
25°C
2.17
2.26
2.17 LSB rms
Full 2
Full 8
Full 0.9
Full 6
2
8
0.9
6
2 V p-p
8 pF
0.9 V
6 kΩ
Full 1.7 1.8 1.9 1.7 1.8
Full 1.7 1.8 1.9 1.7 1.8
Full 1.7
3.5 1.7
1.9 1.7 1.8
1.9 1.7 1.8
3.5 1.7
1.9 V
1.9 V
3.5 V
Full 126 131 169 176 194 202 mA
Full 14
Full 43
20
46
24 mA
49 mA
Full 241 258 323 343 373 392 mW
Full 254
341
394 mW
Full 308
391
439 mW
Full 54
54
54 mW
Full
0.05 0.15
0.05 0.15
0.05 .015 mW
1 The suffix following the part number refers to the model found in the Ordering Guide section.
2 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4 Standby power is measured with a dc input, the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND).
Rev. C | Page 4 of 44

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AD9265 arduino
AD9265
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Electrical
AVDD to AGND
DRVDD to AGND
SVDD to AGND
VIN+, VIN− to AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
VCM to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to AGND
SDIO/DCS to AGND
OEB to AGND
PDWN to AGND
LVDS to AGND
LVDS_RS to AGND
DITHER to AGND
D0 through D15 to AGND
DCO to AGND
Environmental
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0V
−0.3 V to +3.6 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to SVDD +0.3 V
−0.3 V to SVDD +0.3 V
−0.3V to SVDD + 0.3 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−40°C to +85°C
150°C
−65°C to +150°C
Data Sheet
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints and maximizes
the thermal capability of the package.
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown, airflow improves heat dissipation, which
reduces θJA. In addition, metal in direct contact with the package
leads from metal traces, through holes, ground, and power
planes, reduces the θJA.
Table 7. Thermal Resistance
Package Type
Airflow
Velocity
(m/s)
48-Lead LFCSP
(CP-48-8)
0
1.0
2.5
θJA1, 2
24.5
21.4
19.2
θJC1, 3
1.3
θJB1, 4
12.7
Unit
°C/W
°C/W
°C/W
1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-Std 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
ESD CAUTION
Rev. C | Page 10 of 44

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