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PDF AD9262 Data sheet ( Hoja de datos )
| Número de pieza | AD9262 | |
| Descripción | 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to
160 MSPS Dual Continuous Time Sigma-Delta ADC
AD9262
FEATURES
SNR: 83 dB (85 dBFS) to 10 MHz input
SFDR: −87 dBc to 10 MHz input
Noise figure: 15 dB
Input impedance: 1 kΩ
Power: 600 mW
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Selectable bandwidth
2.5 MHz/5 MHz/10 MHz real
5 MHz/10 MHz/20 MHz complex
Output data rate: 30 MSPS to 160 MSPS
Integrated dc and quadrature correction
Integrated decimation filters
Integrated sample rate converter
On-chip PLL clock multiplier
On-chip voltage reference
Offset binary, Gray code, or twos complement data format
Serial control interface (SPI)
APPLICATIONS
Baseband quadrature receivers: CDMA2000, W-CDMA,
multicarrier GSM/EDGE, 802.16x, and LTE
Quadrature sampling instrumentation
Medical equipment
Radio detection and ranging (RADAR)
GENERAL DESCRIPTION
The AD9262 is a dual channel, 16-bit analog-to-digital conver-
ter (ADC) based on a continuous time (CT) sigma-delta (Σ-Δ)
architecture that achieves −87 dBc of dynamic range over a
10 MHz input bandwidth. The integrated features and characteris-
tics unique to the continuous time Σ-Δ architecture significantly
simplify its use and minimize the need for external components.
The AD9262 has a resistive input impedance that relaxes the
requirements of the driver amplifier. In addition, a 32× oversam-
pled fifth-order continuous time loop filter significantly attenuates
out-of-band signals and aliases, reducing the need for external
filters at the input.
An external clock input or the integrated integer-N PLL provides
the 640 MHz internal clock needed for the oversampled conti-
nuous time Σ-Δ modulator. On-chip decimation filters and sample
rate converters reduce the modulator data rate from 640 MSPS to a
user-defined output data rate between 30 MSPS and 160 MSPS,
enabling a more efficient and direct interface.
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
VIN+A
VIN–A
VREF
CFILT
CT Σ-Δ
MODULATOR
LOW-PASS
DECIMATION
FILTER
SAMPLE
RATE
CONVERTER
DC
CORRECT
CMOS
BUFFER
AD9262
QUADRATURE
ERROR
ESTIMATE
GAIN
ADJ
PHASE
ADJ
ORA
D15A
D0A
DCO
VIN–B
VIN+B
CT Σ-Δ
MODULATOR
LOW-PASS
SAMPLE
DECIMATION
RATE
FILTER
CONVERTER
DC
CORRECT
CMOS
BUFFER
D15B
D0B
CLK+
CLK–
PHASE-
LOCKED
LOOP
SERIAL
INTERFACE
ORB
AGND SDIO SCLK CSB DGND
Figure 1
The AD9262 incorporates an integrated dc correction and
quadrature estimation block that corrects for gain and phase
mismatch between the two channels. This functional block
proves invaluable in complex signal processing applications
such as direct conversion receivers.
The digital output data is presented in offset binary, Gray code,
or twos complement format. A data clock output (DCO) is
provided to ensure proper timing with the receiving logic. The
AD9262 has the added feature of interleaving Channel A and
Channel B data onto one 16-bit bus, simplifying on-board routing.
The ADC is available in three different bandwidth options of
2.5 MHz, 5 MHz, and 10 MHz, and operates on a 1.8 V analog
supply and a 1.8 V to 3.3 V digital supply, consuming 600 mW.
The AD9262 is available in a 64-lead LFCSP and is specified
over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. Continuous time Σ-Δ architecture efficiently achieves high
dynamic range and wide bandwidth.
2. Passive input structure reduces or eliminates the require-
ments for a driver amplifier.
3. An oversampling ratio of 32× and high order loop filter
provide excellent alias rejection reducing or eliminating the
need for antialiasing filters.
4. An integrated decimation filter, sample rate converter, PLL
clock multiplier, and voltage reference provide ease of use.
5. Integrated dc correction and quadrature error correction.
6. Operates from a single 1.8 V analog power supply and
1.8 V to 3.3 V output supply.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
AD9262
AC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,
unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 600 kHz2
fIN = 1.2 MHz3
fIN = 2.4 MHz4
fIN = 4.2 MHz
fIN = 8.4 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 600 kHz
fIN = 1.2 MHz
fIN = 2.4 MHz
fIN = 4.2 MHz
fIN = 8.4 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 600 kHz2
fIN = 1.2 MHz3
fIN = 2.4 MHz4
fIN = 4.2 MHz
fIN = 8.4 MHz
NOISE SPECTRAL DENSITY (NSD)
AIN = −2 dBFS
AIN = −40 dBFS
NOISE FIGURE5
TWO-TONE SFDR
fIN1 = 1.8 MHz @ −8 dBFS, fIN2 = 2.1 MHz @ −8 dBFS
fIN1 = 2.1 MHz @ −8 dBFS, fIN2 = 2.4 MHz @ −8 dBFS
fIN1 = 3.7 MHz @ −8 dBFS, fIN2 = 4.2 MHz @ −8 dBFS
fIN1 = 7.2 MHz @ −8 dBFS, fIN2 = 8.4 MHz @ −8 dBFS
CROSSTALK6
ANALOG INPUT BANDWIDTH
APERTURE JITTER
Temp
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
AD9262BCPZ
Min Typ
Max
86 89
89
89
14.5
14.5
−87
−87
<−120
−80
−154.3
−155.4
15.6
−152
−154
−92
−110
2.5
1
AD9262BCPZ-5
Min Typ Max
83 86
86
86
14
14
−87
−87
<−120
−80
−155
−156
15
−152
−154.5
−93
−110
5
1
AD9262BCPZ-10
Min Typ Max
81 83
83
83
13.5
13.5
−87
−87
<−120
−80
−155
−156
15
−153
−154.5
−93
−92.5
−92.5
−110
10
1
Unit
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBFS/Hz
dBFS/Hz
dB
dBc
dBc
dBc
dBc
dB
MHz
ps rms
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Data guaranteed over the full temperature range for the AD9262BCPZ only.
3 Data guaranteed over the full temperature range for the AD9262BCPZ-5 only.
4 Data guaranteed over the full temperature range for the AD9262BCPZ-10 only.
5 Noise figure with respect to 50 Ω. AD9262 internal impedance is 1000 Ω differential. See the AN-835 Application Note for a definition.
6 Crosstalk measured with an input signal on both channels at different frequencies and the leakage of one on to the other.
Rev. A | Page 4 of 32
5 Page 
AD9262
TYPICAL PERFORMANCE CHARACTERISTICS
All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS,
TA = 25°C, output data rate 40 MSPS, unless otherwise noted.
AD9262BCPZ
0 120
BANDWIDTH: 2.5MHz
–20
DATA RATE: 40MSPS
fIN: 600kHz AT –2dBFS
SFDR (dBFS)
100
SNR: 87.9dB
–40 SFDR: 88.2dBc
80
–60 SNR (dBFS)
–80
–100
–120
–140
60
SFDR (dBc)
40
SNR (dB)
20
–160
0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (MHz)
Figure 4. AD9262BCPZ Single-Tone FFT with fIN = 600 kHz
0
BANDWIDTH: 2.5MHz
–20
DATA RATE: 40MSPS
fIN: 1.2MHz AT –2dBFS
SNR: 87.7dB
–40 SFDR: 87.1dBc
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0
INPUT AMPLITUDE (dBFS)
Figure 7. AD9262BCPZ Single-Tone SNR and SFDR vs. Input Amplitude
with fIN = 600 kHz
0
BANDWIDTH: 2.5MHz
–20
DATA RATE: 40MSPS
fIN1: 1.8MHz AT –8dBFS
fIN2: 2.1MHz AT –8dBFS
–40 SFDR: –91.7dBc
–60 –60
–80 –80
–100
–100
–120
–120
–140
–140
–160
0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (MHz)
Figure 5. AD9262BCPZ Single-Tone FFT with fIN = 1.2 MHz
–160
0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (MHz)
Figure 8. AD9262BCPZ Two-Tone FFT with fIN1 = 1.8 MHz, fIN2 = 2.1 MHz
0
BANDWIDTH: 2.5MHz
–20
DATA RATE: 40MSPS
fIN: 2.4MHz AT –2dBFS
SNR: 87.8dB
–40 SFDR: 106.6dBc
–60
–80
–100
–120
–140
–160
0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (MHz)
Figure 6. AD9262BCPZ Single-Tone FFT with fIN = 2.4 MHz
0
–20
–40
SFDR (dBc)
–60
–80
–100
SFDR (dBFS)
–120
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
INPUT AMPLITUDE (dBFS)
Figure 9. AD9262BCPZ Two-Tone SFDR/IMD3 vs. Input Amplitude
with fIN1 = 1.8 MHz, fIN2 = 2.1 MHz
Rev. A | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9262.PDF ] | |
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