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PDF AD9204 Data sheet ( Hoja de datos )
| Número de pieza | AD9204 | |
| Descripción | 1.8V Dual Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9204
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
61.3 dBFS at 9.7 MHz input
61.0 dBFS at 200 MHz input
SFDR
75 dBc at 9.7 MHz input
73 dBc at 200 MHz input
Low power
30 mW per channel at 20 MSPS
63 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
DNL = ±0.11 LSB
Serial port control options
Scalable analog input: 1 V p-p to 2 V p-p differential
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Ultrasound
Radar/LIDAR
PET/SPECT imaging
FUNCTIONAL BLOCK DIAGRAM
AVDD
GND
SDIO SCLK CSB
VIN+A
VIN–A
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
REF
SELECT
SPI
ADC
PROGRAMMING DATA
AD9204
ADC
DIVIDE DUTY CYCLE
1 TO 8 STABILIZER
MODE
CONTROLS
ORA
D9A
D0A
DCOA
DRVDD
ORB
D9B
D0B
DCOB
CLK+ CLK–
SYNC
DCS
PDWN DFS OEB
Figure 1.
PRODUCT HIGHLIGHTS
1. The AD9204 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3. A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO/DATA timing
and offset adjustments, and voltage reference modes.
4. The AD9204 is packaged in a 64-lead RoHS compliant
LFCSP that is pin compatible with the AD9268 16-bit
ADC, the AD9251 and AD9258 14-bit ADCs, and the
AD9231 12-bit ADC, enabling a simple migration path
between 10-bit and 16-bit converters sampling from
20 MSPS to 125 MSPS.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD9204
AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
SIGNAL-TO-NOISE-AND DISTORTION (SINAD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
TWO-TONE SFDR
fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS)
CROSSTALK2
ANALOG INPUT BANDWIDTH
AD9204-20/AD9204-40
AD9204-65
AD9204-80
Temp Min Typ
Max Min Typ Max Min Typ Max Unit
25°C
25°C
Full 61.0
25°C
Full
25°C
61.7
61.6
61.6
61.5
61.4
60.5
61.4
61.0
61.3
61.3
61.3
60.4
61.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
Full 60.1
25°C
Full
25°C
61.5
61.5
61.5
61.2
61.2
59.7
61.2
60
61.1
61.1
61.1
59.5
60
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C 9.9
25°C 9.9
25°C 9.9
25°C
9.8 9.8 Bits
9.8 9.8 Bits
9.8 9.8 Bits
9.6 9.6 Bits
25°C −81
−78 −78 dBc
25°C −81
−78 −78 dBc
Full −65 −64
dBc
25°C −82
−78 −78 dBc
Full −64 dBc
25°C −73 −73 dBc
25°C
25°C
Full 65
25°C
Full
25°C
78
78
78
75
75
64
75
73
75
75
75
64
73
dBc
dBc
dBc
dBc
dBc
dBc
25°C −82
−80 −80 dBc
25°C −82
−80 −80 dBc
Full −71 −70
dBc
25°C −82
−80 −80 dBc
Full −70 dBc
25°C −80 −80 dBc
25°C
Full −100
25°C 700
78
−100
700
78
−100
700
dBc
dBc
MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
Rev. A | Page 5 of 36
5 Page 
Data Sheet
AD9204
Pin No.
49, 50, 53, 54, 59, 60, 63, 64
51, 52
55
56
57
58
61, 62
Mnemonic
AVDD
VIN+A, VIN−A
VREF
SENSE
VCM
RBIAS
VIN−B, VIN+B
Description
1.8 V Analog Supply Pins.
Channel A Analog Inputs.
Voltage Reference Input/Output.
Reference Mode Selection.
Analog output voltage at midsupply to set common mode of the analog inputs.
Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
Channel B Analog Inputs.
Rev. A | Page 11 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9204.PDF ] | |
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