AD9571 Datasheet PDF - Analog Devices
| Part Number | AD9571 | |
| Description | Ethernet Clock Generator | |
| Manufacturers | Analog Devices | |
| Logo |  |
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Ethernet Clock Generator, 10 Clock Outputs
AD9571
FEATURES
Fully integrated VCO/PLL core
0.17 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
0.41 ps rms jitter from 12 kHz to 20 MHz at 125 MHz
Input crystal or clock frequency of 25 MHz
Preset divide ratios for 156.25 MHz, 33.33 MHz,100 MHz, and
125 MHz
Choice of LVPECL or LVDS output format
Integrated loop filter
6 copies of reference clock output
Rates configured via strapping pins
Space saving 6 mm × 6 mm 40-lead LFCSP
0.48 W power dissipation (LVDS operation)
0.69 W power dissipation (LVPECL operation)
3.3 V operation
APPLICATIONS
Ethernet line cards, switches, and routers
SCSI, SATA, and PCI-express
PCI support included
Low jitter, low phase noise clock generation
REFCLK
FUNCTIONAL BLOCK DIAGRAM
REFSEL
CMOS
XTAL
OSC
6 × 25MHz
PFD/CP
3RD-ORDER
LPF
VCO
LVPECL OR
LVDS
1 × 156.25MHz
AD9571
CMOS
2 × 100MHz OR
125MHz
1 × 33.33MHz
FORCE_LOW
FREQSEL
Figure 1.
GENERAL DESCRIPTION
The AD9571 provides a multioutput clock generator function
comprising a dedicated PLL core that is optimized for Ethernet
line card applications. The integer-N PLL design is based on the
Analog Devices, Inc., proven portfolio of high performance, low
jitter frequency synthesizers to maximize network performance.
Other applications with demanding phase noise and jitter
requirements also benefit from this part.
The PLL section consists of a low noise phase frequency
detector (PFD), a precision charge pump (CP), a low phase
noise voltage controlled oscillator (VCO), and a preprogrammed
feedback divider and output divider. By connecting an external
crystal or reference clock to the REFCLK pin, frequencies up to
156.25 MHz can be locked to the input reference.
Each output divider and feedback divider ratio is prepro-
grammed for the required output rates. No external loop filter
components are required, thus conserving valuable design time
and board space.
The AD9571 is available in a 40-lead 6 mm × 6 mm lead frame
chip scale package and can be operated from a single 3.3 V
supply. The operating temperature range is −40°C to +85°C.
OPTIONAL
CX-4 PHY
XAUI
48 + 2 SWITCH/MAC
CPU
ISLAND
6 × 25MHz
2 × 125MHz
1 × 156.25MHz
1 × 33.33MHz
AD9571
2 × OCTAL
GbE PHY
2 × OCTAL
GbE PHY
2 × OCTAL 2 × OCTAL
GbE PHY GbE PHY
Figure 2. Typical Application
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for its use,norforanyinfringements ofpatents or other
rightsofthirdpartiesthat mayresult fromitsuse.Specificationssubjecttochangewithoutnotice. No
license isgranted by implication or otherwise under anypatent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
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AD9571
Parameter
PLL Noise (125 MHz LVPECL Output)
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 10 MHz
@ 30 MHz
PLL Noise (100 MHz LVPECL Output)
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 10 MHz
@ 30 MHz
Phase Noise (33.33 MHz CMOS Output)
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 5 MHz
Phase Noise (25 MHz CMOS Output)
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 5 MHz
Spurious Content1
PLL Figures of Merit
Min
Typ
Max Unit
Test Conditions/Comments
−121
−127
−128
−148
−152
−153
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
−115
−121
−128
−148
−150
−150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
−131
−138
−139
−151
−152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−133
−143
−147
−148
−148
−70
−217.5
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
dBc/Hz
Dominant amplitude with all outputs active
1 When the 33.33 MHz, 100 MHz, and 125 MHz clocks are enabled simultaneously, a worst-case −50 dBc spurious content may be presented on Pin 21 and Pin 22 only.
LVDS CLOCK OUTPUT JITTER
Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 2.
Jitter Integration
Bandwidth (Typ)
12 kHz to 20 MHz
100 MHz
0.50
1.875 MHz to 20 MHz
200 kHz to 10 MHz
0.30
125 MHz1,
33.33 MHz = Off/On
0.41/0.77
156.25 MHz
0.41
Unit
ps rms
0.17 ps rms
0.24/0.66
ps rms
Test Conditions/Comments
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 1 × 33.33 MHz
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 1 × 33.33 MHz
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 1 × 33.33 MHz
1 The typical 125 MHz rms jitter data collected from the differential pair of Pin 21 and Pin 22, unless otherwise noted.
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