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AD9508 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9508
Beschreibung 1.65 GHz Clock Fanout Buffer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9508 Datasheet, Funktion
Data Sheet
1.65 GHz Clock Fanout Buffer with
Output Dividers and Delay Adjust
AD9508
FEATURES
1.65 GHz differential clock inputs/outputs
10-bit programmable dividers, 1 to 1024, all integers
Up to 4 differential outputs or 8 CMOS outputs
Pin strapping capability for hardwired programming at
power-up
<115 fs rms broadband random jitter (see Figure 25)
Additive output jitter: 41 fs rms typical (12 kHz to 20 MHz)
Excellent output-to-output isolation
Automatic synchronization of all outputs
Single 2.5 V/3.3 V power supply
Internal LDO (low drop-out) voltage regulator for enhanced
power supply immunity
Phase offset select for output-to-output coarse delay adjust
3 programmable output logic levels, LVDS, HSTL, and CMOS
Serial control port (SPI/I2C) or pin-programmable mode
Space-saving 24-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
GENERAL DESCRIPTION
The AD9508 provides clock fanout capability in a design that
emphasizes low jitter to maximize system performance. This
device benefits applications like clocking data converters with
demanding phase noise and low jitter requirements.
There are four independent differential clock outputs, each with
various types of logic levels available. Available logic types
include LVDS (1.65 GHz), HSTL (1.65 GHz), and 1.8 V CMOS
(250 MHz). In 1.8 V CMOS output mode, the differential output
becomes two CMOS single-ended signals. The CMOS outputs
are 1.8 V logic levels, regardless of the operating supply voltage.
FUNCTIONAL BLOCK DIAGRAM
AD9508
CLK
CLK
SCLK/SCL/S0
SDIO/SDA/S1
SDO/S3
CS/S2
CONTROL
INTERFACE
SPI/I2C/PINS
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
PIN CONTROL RESET
Figure 1.
SYNC
Each output has a programmable divider that can be bypassed
or be set to divide by any integer up to 1024. In addition, the
AD9508 supports a coarse output phase adjustment between
the outputs.
The device can also be pin programmed for various fixed
configurations at power-up without the need for SPI or I2C
programming.
The AD9508 is available in a 24-lead LFCSP and operates from
a either a single 2.5 V or 3.3 V supply. The temperature range is
−40°C to +85°C.
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD9508 Datasheet, Funktion
Data Sheet
AD9508
CLOCK INPUTS AND OUTPUT DC SPECIFICATIONS
Table 2.
Parameter
CLOCK INPUTS
Differential Mode
Input Frequency
Input Sensitivity
Input Common-Mode Voltage
Input Voltage Offset
DC-Coupled Input Common-
Mode Range
Pulse Width
Low
High
Input Resistance (Single-Ended)
Input Capacitance
Input Bias Current (Each Pin)
CMOS CLOCK MODE (SINGLE-ENDED)
Input Frequency
Input Voltage
High
Low
Input Current
High
Low
Input Capacitance
LVDS CLOCK OUTPUTS
Output Frequency
Output Voltage Differential
Delta VOD
Offset Voltage
Delta VOS
Short-Circuit Current
LVDS Duty Cycle
HSTL CLOCK OUTPUTS
Output Frequency
Differential Output Voltage
Common-Mode Output Voltage
HSTL Duty Cycle
Symbol Min
Typ Max
Unit Test Conditions/Comments
VICM
VCMR
CIN
VIH
VIL
IINH
IINL
CIN
VOD
ΔVOD
VOS
ΔVOS
ISA, ISB
VO
VOCM
0
1650
MHz Differential input
360
2200
mV p-p As measured with a differential probe; jitter
performance improves with higher slew
rates (greater voltage swing)
0.95 1.05 1.15 V Input pins are internally self biased, which
enables ac coupling
30 mV
0.58 1.67 V This is the allowable common-mode
voltage range when dc-coupled
303 ps
303 ps
5.0 7 9
kΩ
2 pF
100 400 µA Full input swing
2.5 V or 3.3 V CMOS only; for 1.8 V CMOS,
use (ac-coupled) differential input mode
250 MHz
VDD/2 + 0.15
V
VDD/2 − 0.15 V
247
1.125
45
39
859
905
45
40
1
142
2
1650
375 454
50
1.18 1.375
50
13.6 24
55
61
50.1
1650
925 978
940 971
55
60
50.9
µA
µA
pF
Termination = 100 Ω differential (OUTx, OUTx)
MHz
mV VOH − VOL measurement across a differential
pair at the default amplitude setting with
output driver not toggling; see Figure 6 for
variation over frequency
mV This is the absolute value of the difference
between VOD when the normal output is high
vs. when the complementary output is high
V (VOH + VOL)/2 across a differential pair
mV This is the absolute value of the difference
between VOS when the normal output is high
vs. when the complementary output is high
mA Each pin (output shorted to GND)
% Up to 750 MHz input
% 750 MHz to1500 MHz input
% 1650 MHz input
100 Ω across differential pair; default
amplitude setting
MHz
mV VOH − VOL with output driver static
mV (VOH + VOL)/2 with output driver static
% Up to 750 MHz input
% 750 MHz to 1500 MHz input
% 1650 MHz input
Rev. F | Page 5 of 40

6 Page









AD9508 pdf, datenblatt
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 10.
Parameter
Supply Voltage (VDD)
Maximum Digital Input Voltage
CLK and CLK
Maximum Digital Output Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
3.6 V
−0.5 V to VDD + 0.5 V
−0.5 V to VDD + 0.5 V
−0.5 V to VDD + 0.5 V
−65°C to +150°C
−40°C to +85°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
The following equation determines the junction temperature on
the application PCB:
TJ = TCASE + (ΨJT × PD)
where:
TJ is the junction temperature (°C).
TCASE is the case temperature (°C) measured by the customer at
the top center of the package.
ΨJT is the value as indicated in Table 11.
PD is the power dissipation.
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order approxi-
mation of TJ by the following equation:
TJ = TA + (θJA × PD)
where TA is the ambient temperature (°C).
AD9508
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Values of θJB are provided for package comparison and PCB
design considerations.
THERMAL CHARACTERISTICS
Thermal characteristics established using JEDEC51-7 and
JEDEC51-5 2S2P test boards.
Table 11. Thermal Characteristics, 24-Lead LFCSP
Thermal Characteristic
(JEDEC51-7 and JEDEC51-5 2S2P
Symbol Test Boards1)
Value2 Unit
θJA Junction-to-ambient thermal
43.5 °C/W
resistance per JEDEC JESD51-2 (still
air)
θJMA Junction-to-ambient thermal
40 °C/W
resistance, 1.0 m/sec airflow per
JEDEC JESD51-6 (moving air)
θJMA Junction-to-ambient thermal
38.5 °C/W
resistance, 2.5 m/sec airflow per
JEDEC JESD51-6 (moving air)
θJB Junction-to-board thermal
16.2 °C/W
resistance per JEDEC JESD51-8 (still
air)
θJC
Junction-to-case thermal resistance 7.1
°C/W
(die-to-heat sink) per MIL-STD-883,
Method 1012.1
ΨJT Junction-to-top-of-package
0.33 °C/W
characterization parameter per
JEDEC JESD51-2 (still air)
1 The exposed pad on the bottom of the package must be soldered to ground
(VSS) to achieve the specified thermal performance.
2 Results are from simulations. The PCB is a JEDEC multilayer type. Thermal
performance for actual applications requires careful inspection of the
conditions in the application to determine if they are similar to those
assumed in these calculations.
ESD CAUTION
Rev. F | Page 11 of 40

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