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PDF AD9913 Data sheet ( Hoja de datos )
| Número de pieza | AD9913 | |
| Descripción | Low Power 250 MSPS 10-Bit DAC 1.8V CMOS Direct Digital Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
Low Power 250 MSPS 10-Bit DAC 1.8 V
CMOS Direct Digital Synthesizer
AD9913
FEATURES
50 mW at up to 250 MSPS internal clock speed
100 MHz analog output
Integrated 10-bit DAC
0.058 Hz or better frequency resolution
0.022° phase tuning resolution
Programmable modulus in frequency equation
Phase noise ≤ –135 dBc per Hz @ 1 kHz offset (DAC output)
(<115 dBc per Hz when using on-board PLL multiplier)
Excellent dynamic performance
>80 dB SFDR @ 100 MHz (±100 kHz offset) AOUT
Automatic linear frequency sweeping capability
8 frequency or phase offset profiles
1.8 V power supply
Software and hardware controlled power-down
Parallel and serial programming options
32-lead LFCSP package
Optional PLL REF_CLK multiplier
Internal oscillator (can be driven by a single crystal)
Phase modulation capability
APPLICATIONS
Portable and handheld equipment
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
GENERAL DESCRIPTION
The AD9913 is a complete direct digital synthesizer (DDS)
designed to meet the stringent power consumption limits of
portable, handheld, and battery-powered equipment. The
AD9913 features a 10-bit digital-to-analog converter (DAC)
operating up to 250 MSPS. The AD9913 uses advanced DDS
technology, coupled with an internal high speed, high
performance DAC to form a complete, digitally-program-
mable, high frequency synthesizer capable of generating a
frequency agile analog output sinusoidal waveform at up to
100 MHz.
The AD9913 provides fast frequency hopping and fine tuning
resolution. The AD9913 also offers fine resolution phase offset
control. Control words are loaded into the AD9913 through the
serial or parallel I/O port. The AD9913 also supports a user-
defined linear sweep mode of operation for generating highly
linearized swept waveforms of frequency. To support various
methods of generating a system clock, the AD9913 includes an
oscillator, allowing a simple crystal to be used as the frequency
reference, as well as a high speed clock multiplier to convert the
reference clock frequency up to the full system clock rate. For
power saving considerations, many of the individual blocks of
the AD9913 can be powered down when not in use.
The AD9913 operates over the extended industrial temperature
range of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
AD9913
DDS
10-BIT
DAC
REF_CLK INPUT
CIRCUITRY
TIMING AND
CONTROL LOGIC
USER INTERFACE
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD9913
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
AVDD (1.8 V), DVDD (1.8 V), and DVDD_I/O = 1.8 V ± 5%, T = 25°C, RSET = 4.64 kΩ, DAC full-scale current = 2 mA, external
reference clock frequency = 250 MHz with REF_CLK multiplier disabled, unless otherwise noted.
Table 1.
Parameter
REF_CLK INPUT CHARACTERISTICS
Frequency Range
REF_CLK Multiplier
REF_CLK Input Divider Frequency
VCO Oscillation Frequency
PLL Lock Time
External Crystal Mode
CMOS Mode
Input Capacitance
Input Impedance (Differential)
Input Impedance (Single-Ended)
Duty Cycle
REF_CLK Input Level
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
AC Voltage Compliance Range
SPURIOUS-FREE DYNAMIC RANGE
SERIAL PORT TIMING CHARACTERISTICS
SCLK Frequency
SCLK Pulse Width
SCLK Rise/Fall Time
Data Setup Time to SCLK
Data Hold Time to SCLK
Data Valid Time in Read Mode
PARALLEL PORT TIMING CHARACTERISTICS
PCLK Frequency
PCLK Pulse Width
PCLK Rise/Fall Time
Address/Data Setup Time to PCLK
Address/Data Hold Time to PCLK
Data Valid Time in Read Mode
IO_UPDATE/PROFILE(2:0) TIMING
Setup Time to SYNC_CLK
Hold Time to SYNC_CLK
Conditions/Comments
Min Typ Max Unit
Disabled
Enabled
Full temperature range
VCO1
VCO2
25 MHz reference clock, 10× PLL
VIH
VIL
Refer to Figure 6
Low
High
Low
High
250 MHz
250 MHz
83 MHz
16 250 MHz
100 250 MHz
60 µs
25 MHz
0.9 V
0.65 V
3 pF
2.7 kΩ
1.35 kΩ
45 55 %
355 1000 mV p-p
4.6 mA
−14 −6 %FS
+0.1 µA
−0.4 +0.4 LSB
−0.5 +0.5 LSB
±400
mV
32 MHz
17.5 ns
3.5 ns
2 ns
5.5 ns
0 ns
22 ns
33 MHz
10 ns
20 ns
2 ns
3.0 ns
0.3 ns
8 ns
0.5 ns
1 SYNC_CLK cycles
Rev. B | Page 3 of 32
5 Page 
Data Sheet
–50
–55
–60
–65
–70
–75
–80
–85
–90
0
39.88%
10.21%
26.58%
50 100 150 200
SYSTEM CLOCK (MHz)
250
Figure 10. SFDR vs. System Clock Frequency (PLL Bypassed)
–100
–110
–120
92.3MHz
48.9MHz
23.1MHz
6.1MHz
–130
–140
–150
–160
–170
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (MHz)
Figure 11. Residual Phase Noise vs. fOUT (PLL Bypassed)
AD9913
−50
−60
−70
−80
−90
−100
−110
99MHz
49MHz
−120
−130
−140
25MHz
12.5MHz
−150
100 1k 10k 100k 1M 10M 100M
FREQUENCY (MHz)
Figure 12. Absolute Phase Noise vs. fOUT Using the Internal PLL
(REF_CLK 25 MHz × 10 = 250 MHz Using PLL)
–50
PLL ×10
–55 REFSPUR
–60
BYPASS
–65
–70
–75
–80
–85
–90
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
fOUT (% of System Clock)
Figure 13. SFDR Without the Internal PLL
(REF_CLK = 25 MHz × 10 = 250 MHz Using PLL, 4 mA DAC Full-Scale Current)
Rev. B | Page 9 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9913.PDF ] | |
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