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AD9613 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9613
Beschreibung 1.8V Dual Analog-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9613 Datasheet, Funktion
Data Sheet
12-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Dual Analog-to-Digital Converter (ADC)
AD9613
FEATURES
SNR = 69.6 dBFS at 185 MHz fIN and 250 MSPS
SFDR = 86 dBc at 185 MHz fIN and 250 MSPS
−149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and
250 MSPS
Total power consumption: 770 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
GENERAL DESCRIPTION
The AD9613 is a dual 12-bit, analog-to-digital converter (ADC)
with sampling speeds of up to 250 MSPS. The AD9613 is designed
to support communications applications where low cost, small
size, wide bandwidth, and versatility are desired.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of user-
selectable input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer (DCS) is provided to
compensate for variations in the ADC clock duty cycle,
allowing the converters to maintain excellent performance.
The ADC output data is routed directly to the two external 12-bit
LVDS output ports and formatted as either interleaved or channel
multiplexed.
Flexible power-down options allow significant power savings,
when desired.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
VIN+A
VIN–A
VCM
VIN+B
VIN–B
PIPELINE 12
12-BIT
ADC
AD9613
PARALLEL
DDR LVDS
PIPELINE 12
12-BIT
AND
DRIVERS
ADC
REFERENCE
SERIAL PORT
1 TO 8
CLOCK
DIVIDER
D0±.
.
.
.
.
D11±
DCO±
OR±
OEB
PDWN
SCLK SDIO CSB
CLK+ CLK– SYNC
NOTES
1. THE D0± TO D11± PINS REPRESENT BOTH THE CHANNEL A
AND CHANNEL B LVDS OUTPUT DATA.
Figure 1.
Programming for setup and control is accomplished using a
3-wire SPI-compatible serial interface.
The AD9613 is available in a 64-lead LFCSP and is specified
over the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated dual, 12-bit, 170 MSPS/210 MSPS/250 MSPS ADCs.
2. Fast overrange and threshold detect.
3. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
4. SYNC input allows synchronization of multiple devices.
5. 3-pin, 1.8 V SPI port for register programming and register
readback.
6. Pin compatibility with the AD9643, allowing a simple
migration up to 14 bits, and with the AD6649 and the AD6643.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD9613 Datasheet, Funktion
Data Sheet
AD9613
Parameter1
TWO-TONE SFDR
fIN = 184.12 MHz (−7 dBFS),
187.12 MHz (−7 dBFS)
CROSSTALK2
FULL POWER BANDWIDTH3
AD9613-170
AD9613-210
Temp Min Typ Max Min Typ Max
25°C 88
Full 95
25°C 1000
88
95
1000
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
3 Full power bandwidth is the bandwidth of operation where typical ADC performance can be achieved.
AD9613-250
Min Typ Max
88
95
1000
Unit
dBc
dB
MHz
Rev. C | Page 5 of 36

6 Page









AD9613 pdf, datenblatt
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Electrical
AVDD to AGND
DRVDD to AGND
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VCM to AGND
CSB to AGND
SCLK to AGND
SDIO to AGND
OEB to AGND
PDWN to AGND
OR+/OR− to AGND
D0−/D0+ Through D11−/D11+ to
AGND
DCO+/DCO− to AGND
Environmental
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD9613
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the
printed circuit board (PCB) increases the reliability of the
solder joints, maximizing the thermal capability of the package.
Typical θJA is specified for a 4-layer PCB with solid ground
plane. As shown in Figure 40, airflow increases heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes reduces the θJA.
Table 7. Thermal Resistance
Package Type
Airflow
Velocity
(m/sec)
64-Lead LFCSP
9 mm × 9 mm
(CP-64-4)
0
1.0
2.0
θJA1, 2
26.8
21.6
20.2
θJC1, 3
1.14
θJB1, 4
10.4
1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-Std 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
Unit
°C/W
°C/W
°C/W
ESD CAUTION
Rev. C | Page 11 of 36

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