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AD9690 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9690
Beschreibung Analog-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9690 Datasheet, Funktion
Data Sheet
14-Bit, 1 GSPS/500 MSPS JESD204B,
Analog-to-Digital Converter
AD9690
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
2.0 W total power at 1 GSPS (default settings)
1.5 W total power at 500 MSPS (default settings)
SFDR = 85 dBFS at 340 MHz, 80 dBFS at 985 MHz
SNR = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS),
60.5 dBFS at 985 MHz
ENOB = 10.8 bits at 10 MHz
DNL = ±0.5 LSB
INL = ±2.5 LSB
Noise density = −154 dBFS/Hz at 1 GSPS
1.25 V, 2.5 V, and 3.3 V dc supply operation
No missing codes
Internal ADC voltage reference
Flexible input range
AD9690-1000: 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal)
AD9690-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
Programmable termination impedance
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
2 GHz usable analog input full power bandwidth
Amplitude detect bits for efficient AGC implementation
2 integrated wideband digital processors
12-bit NCO, up to 4 cascaded half-band filters
Differential clock input
Integer clock divide by 1, 2, 4, or 8
Flexible JESD204B lane configurations
Small signal dither
APPLICATIONS
Communications
Multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
General-purpose software radios
Ultrawideband satellite receivers
Instrumentation
Radars
Signals intelligence (SIGINT)
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
Wideband digital predistortion
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD
(1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V)
VIN+
VIN–
BUFFER
ADC 14
CORE
FD
DDC
4 SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
V_1P0
CLK+
CLK–
CONTROL
REGISTERS
CLOCK
GENERATION
JESD204B
SUBCLASS 1
CONTROL
FAST
DETECT
SYNCINB±
SYSREF±
÷2
SPI CONTROL
÷4
PDWN/
÷8 AD9690 STBY
AGND DRGND DGND SDIO SCLK CSB
Figure 1.
PRODUCT HIGHLIGHTS
1. Wide full power bandwidth supports IF sampling of signals
up to 2 GHz.
2. Buffered inputs with programmable input termination eases
filter design and implementation.
3. Two integrated wideband decimation filters and numerically
controlled oscillator (NCO) blocks supporting multiband
receivers.
4. Flexible serial port interface (SPI) controls various product
features and functions to meet specific system requirements.
5. Programmable fast overrange detection.
6. 9 mm × 9 mm, 64-lead LFCSP.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD9690 Datasheet, Funktion
Data Sheet
AD9690
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Voltage
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUTS
Differential Input Voltage Range (Programmable)
Common-Mode Voltage (VCM)
Differential Input Capacitance
Analog Input Full Power Bandwidth
POWER SUPPLY
AVDD1
AVDD2
AVDD3
AVDD1_SR
DVDD
DRVDD
SPIVDD
IAVDD1
IAVDD2
IAVDD3
IAVDD1_SR
IDVDD1
IDRVDD1
ISPIVDD
POWER CONSUMPTION
Total Power Dissipation (Including Output Drivers)1
Power-Down Dissipation
Standby2
Temperature
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9690-500
Min Typ Max
14
AD9690-1000
Min Typ Max
14
Unit
Bits
Guaranteed
−0.3 0
+0.3
−6 0
+6
−0.6 ±0.5 +0.7
−4.5 ±2.5 +5.0
Guaranteed
−0.31 0
+0.31
−6 0
+6
−0.7 ±0.5 +0.8
−5.7 ±2.5 +6.9
% FSR
% FSR
LSB
LSB
−9 −14 ppm/°C
±25
±13.8
ppm/°C
1.0 1.0 V
2.06 2.63 LSB rms
1.46 2.06 2.06 1.46 1.70 1.94 V p-p
2.05 2.05 V
1.5 1.5 pF
2 2 GHz
1.22 1.25 1.28 1.22 1.25 1.28 V
2.44 2.5 2.56 2.44 2.5
2.56 V
3.2 3.3 3.4 3.2 3.3 3.4 V
1.22 1.25 1.28 1.22 1.25 1.28 V
1.22 1.25 1.28 1.22 1.25 1.28 V
1.22 1.25 1.28 1.22 1.25 1.28 V
1.7 1.8 3.4 1.7 1.8 3.4 V
245 286
370 409 mA
279 343
370 456 mA
61 75
83 100 mA
16 18
15 18 mA
73 107
129 159 mA
109 181
147 175 mA
56
5 6 mA
1.5 2.0 W
600 700 mW
900
1100
mW
1 Default mode. No DDCs used. 500 MSPS is L = 2, M = 1, and F = 1; 1000 MSPS is L = 4, M = 1, and F = 1. Power dissipation on DRVDD changes with lane rate and
number of lanes used. Care must be taken to ensure that the serial line rate for a given configuration is within the supported range of 3.125 Gbps to 12.5 Gbps.
2 Can be controlled by the SPI.
Rev. A | Page 5 of 78

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AD9690 pdf, datenblatt
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Electrical
AVDD1 to AGND
AVDD1_SR to AGND
AVDD2 to AGND
AVDD3 to AGND
DVDD to DGND
DRVDD to DRGND
SPIVDD to AGND
AGND to DRGND
VIN± to AGND
SCLK, SDIO, CSB to AGND
PDWN/STBY to AGND
Environmental
Operating Temperature Range
Junction Temperature Range
Storage Temperature Range
(Ambient)
Rating
1.32 V
1.32 V
2.75 V
3.63 V
1.32 V
1.32 V
3.63 V
−0.3 V to +0.3 V
3.2 V
−0.3 V to SPIVDD + 0.3 V
−0.3 V to SPIVDD + 0.3 V
−40°C to +85°C
−40°C to +115°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
AD9690
THERMAL CHARACTERISTICS
Typical θJA, θJB, and θJC are specified vs. the number of printed
circuit board (PCB) layers in different airflow velocities (in m/sec).
Airflow increases heat dissipation effectively reducing θJA and
θJB. In addition, metal in direct contact with the package leads
and exposed pad from metal traces, through holes, ground, and
power planes, reduces θJA. Thermal performance for actual
applications requires careful inspection of the conditions in
an application. The use of appropriate thermal management
techniques is recommended to ensure that the maximum
junction temperature does not exceed the limits shown in Table 6.
Table 7. Thermal Resistance Values
PCB
Type
Airflow
Velocity
(m/sec) θJA
ΨJB
JEDEC
2s2p
Board
0.0
1.0
2.5
17.81, 2
15.61, 2
15.01, 2
6.31, 3
5.91, 3
5.71, 3
θJC_TOP
4.71, 4
N/A5
N/A5
θJC_BOT
1.21, 4
Unit
°C/W
°C/W
°C/W
1 Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per JEDEC JESD51-8 (still air).
4 Per MIL-STD 883, Method 1012.1.
5 N/A means not applicable.
ESD CAUTION
Rev. A | Page 11 of 78

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