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AD9680 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9680
Beschreibung Dual Analog-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9680 Datasheet, Funktion
Data Sheet
14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS
JESD204B, Dual Analog-to-Digital Converter
AD9680
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
1.65 W total power per channel at 1 GSPS (default settings)
SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz
SNR at 1 GSPS = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS),
60.5 dBFS at 1 GHz (AIN = −1.0 dBFS)
ENOB = 10.8 bits at 10 MHz
DNL = ±0.5 LSB
INL = ±2.5 LSB
Noise density = −154 dBFS/Hz at 1 GSPS
1.25 V, 2.5 V, and 3.3 V dc supply operation
No missing codes
Internal ADC voltage reference
Flexible input range: 1.46 V p-p to 1.94 V p-p
AD9680-1250: 1.58 V p-p nominal
AD9680-1000 and AD9680-820: 1.70 V p-p nominal
AD9680-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
Programmable termination impedance
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
2 GHz usable analog input full power bandwidth
95 dB channel isolation/crosstalk
Amplitude detect bits for efficient AGC implementation
2 integrated wideband digital processors per channel
12-bit NCO, up to 4 half-band filters
Differential clock input
Integer clock divide by 1, 2, 4, or 8
Flexible JESD204B lane configurations
Small signal dither
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
General-purpose software radios
Ultrawideband satellite receivers
Instrumentation
Radars
Signals intelligence (SIGINT)
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD
(1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V)
VIN+A
VIN–A
FD_A
FD_B
VIN+B
VIN–B
V_1P0
CLK+
CLK–
BUFFER
ADC
CORE 14
SIGNAL
MONITOR
DDC
4
14
ADC
CORE
BUFFER
DDC
CONTROL
REGISTERS
FAST
DETECT
CLOCK
GENERATION
SIGNAL
MONITOR
JESD204B
SUBCLASS 1
CONTROL
÷2 SPI CONTROL
÷4
÷8 AD9680
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
SYNCINB±
SYSREF±
PDWN/
STBY
AGND DRGND DGND SDIO SCLK CSB
Figure 1.
PRODUCT HIGHLIGHTS
1. Wide full power bandwidth supports IF sampling of signals
up to 2 GHz.
2. Buffered inputs with programmable input termination eases
filter design and implementation.
3. Four integrated wideband decimation filters and numerically
controlled oscillator (NCO) blocks supporting multiband
receivers.
4. Flexible serial port interface (SPI) controls various product
features and functions to meet specific system requirements.
5. Programmable fast overrange detection.
6. 9 mm × 9 mm, 64-lead LFCSP.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD9680 Datasheet, Funktion
Data Sheet
AD9680
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity
(DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE
REFERENCE
Voltage
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUTS
Differential Input Voltage
Range (Programmable)
Common-Mode Voltage
(VCM)
Differential Input
Capacitance1
Analog Input Full Power
Bandwidth
POWER SUPPLY
AVDD1
AVDD2
AVDD3
AVDD1_SR
DVDD
DRVDD
SPIVDD
IAVDD1
IAVDD2
IAVDD3
IAVDD1_SR
IDVDD2
IDRVDD1
IDRVDD (L = 2 Mode)
ISPIVDD
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
AD9680-500
Min Typ Max
14
AD9680-820
Min Typ Max
14
AD9680-1000
Min Typ Max
14
Guaranteed
−0.3 0 +0.3
0 0.3
−6 0 +6
1 5.1
−0.6 ±0.5 +0.7
Guaranteed
−0.3 0
+0.3
0 0.23
−6 0
+6
1 5.5
−0.7 ±0.5 +0.8
Guaranteed
−0.31 0
+0.31
0 0.23
−6 0
+6
1 4.5
−0.7 ±0.5 +0.8
−4.5 ±2.5 +5.0 −3.3 ±2.5 +4.3 −5.7 ±2.5 +6.9
−3 −10
±25 ±54
−12
±13.8
1.0 1.0
1.0
2.06 2.46
2.63
1.46 2.06 2.06 1.46 1.70 1.94 1.46 1.70 1.94
2.05 2.05
2.05
1.5 1.5
1.5
22
2
1.22 1.25 1.28 1.22 1.25 1.28 1.22
2.44 2.50 2.56 2.44 2.50 2.56 2.44
3.2 3.3 3.4 3.2 3.3 3.4 3.2
1.22 1.25 1.28 1.22 1.25 1.28 1.22
1.22 1.25 1.28 1.22 1.25 1.28 1.22
1.22 1.25 1.28 1.22 1.25 1.28 1.22
1.7 1.8 3.4 1.7 1.8 3.4 1.7
435 467
605 660
395 463
490 545
87 101
125 140
15 22
15 18
145 152
205 246
190 237
200 240
140 N/A3
56
56
1.25 1.28
2.50 2.56
3.3 3.4
1.25 1.28
1.25 1.28
1.25 1.28
1.8 3.4
685 720
595 680
125 142
16 18
208 269
200 225
N/A3
56
AD9680-1250
Min Typ Max
14
Unit
Bits
Guaranteed
−0.31 0
+0.31
0 0.3
−6 0
+6
1 4.5
−0.8 ±0.5 +0.8
% FSR
% FSR
% FSR
% FSR
LSB
−6 ±3 +6 LSB
−15 ppm/°C
92 ppm/°C
1.0 V
3.45 LSB rms
1.46 1.58 1.94 V p-p
2.05 V
1.5 pF
2 GHz
1.22 1.25 1.28 V
2.44 2.50 2.56 V
3.2 3.3 3.4 V
1.22 1.25 1.28 V
1.22 1.25 1.28 V
1.22 1.25 1.28 V
1.7 1.8 3.4 V
785 880 mA
675 780 mA
125 142 mA
17 20 mA
250 325 mA
220 300 mA
N/A3 mA
56
mA
Rev. C | Page 5 of 97

6 Page









AD9680 pdf, datenblatt
Data Sheet
CLK–
CLK+
SYSREF–
SYSREF+
tSU_SR
tH_SR
Figure 3. SYSREF± Setup and Hold Timing
AD9680
CSB
tDS tHIGH
tS tDH
tLOW
tCLK
tACCESS
tH
SCLK DON’T CARE
DON’T CARE
SDIO DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7
D7 D6 D3 D2 D1 D0 DON’T CARE
Figure 4. Serial Port Interface Timing Diagram
Rev. C | Page 11 of 97

12 Page





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