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AD8114 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8114
Beschreibung 16 x 16 Crosspoint Switches
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
AD8114 Datasheet, Funktion
Data Sheet
FEATURES
16 × 16 high speed nonblocking switch arrays
AD8114; G = 1
AD8115; G = 2
Serial or parallel programming of switch array
Serial data out allows daisy-chaining of multiple
16 × 16 arrays to create larger switch arrays
High impedance output disable allows connection of
multiple devices without loading the output bus
For smaller arrays see the AD8108/AD8109 (8 × 8) or
AD8110/AD8111 (16 × 8) switch arrays
Complete solution
Buffered inputs
Programmable high impedance outputs
16 output amplifiers, AD8114 (G = 1), AD8115 (G = 2)
Drives 150 Ω loads
Excellent video performance
25 MHz, 0.1 dB gain flatness
0.05%/0.05° differential gain/differential phase error
(RL = 150 Ω)
Excellent ac performance
−3 dB bandwidth: 225 MHz
Slew rate: 375 V/µs
Low power of 700 mW (2.75 mW per point)
Low all hostile crosstalk of −70 dB at 5 MHz
Reset pin allows disabling of all outputs (connected through
a capacitor to ground provides power-on reset capability)
100-lead LQFP (14 mm × 14 mm)
APPLICATIONS
Routing of high speed signals, including
Video (NTSC, PAL, S, SECAM, YUV, RGB)
Compressed video (MPEG, wavelet)
3-level digital video (HDB3)
Data communications
Telecommunications
GENERAL DESCRIPTION
The AD8114/AD8115 are high speed, 16 × 16 video crosspoint
switch matrices. They offer a −3 dB signal bandwidth greater than
200 MHz and channel switch times of less than 50 ns with 1%
settling. With −70 dB of crosstalk and −98 dB isolation (at 5 MHz),
the AD8114/AD8115 are useful in many high speed applications.
Low Cost, 225 MHz,
16 × 16 Crosspoint Switches
AD8114/AD8115
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3 D4
CLK
DATA IN
UPDATE
CE
RESET
80-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL LOADING
A0
A1
A2
A3
DATA
OUT
80
PARALLEL LATCH
80
DECODE
16 × 5:16 DECODERS
SET
INDIVIDUAL
OR RESET
ALL OUTPUTS
TO "OFF"
16
AD8114/AD8115
OUTPUT
256 BUFFER
G = +1,
G = +2
16 INPUTS
SWITCH
MATRIX
16
OUTPUTS
Figure 1.
The differential gain and differential phase of better than 0.05%
and 0.05°, respectively, along with a 0.1 dB flatness out to 25 MHz
while driving a 75 Ω back-terminated load, make the AD8114/
AD8115 ideal for all types of signal switching.
The AD8114/AD8115 include 16 independent output buffers
that can be placed into a high impedance state for paralleling
crosspoint outputs so that off channels do not load the output bus.
The AD8114 has a gain of 1, while the AD8115 offers a gain of 2.
They operate on voltage supplies of ±5 V while consuming only
70 mA of idle current. The channel switching is performed via a
serial digital control (which can accommodate daisy-chaining of
several devices) or via a parallel control, allowing updating of an
individual output without reprogramming the entire array.
The AD8114/AD8115 is packaged in a 100-lead LQFP and is
available over the extended industrial temperature range of
−40°C to +85°C.
Rev. C
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1998–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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AD8114 Datasheet, Funktion
AD8114/AD8115
TIMING CHARACTERISTICS (PARALLEL)
Table 4. Timing Characteristics
Parameter
Data Setup Time
CLK Pulse Width
Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall Times
RESET Time
Data Sheet
Symbol
t1
t2
t3
t4
t5
t6
Min Typ
20
100
20
100
0
50
Max Unit
ns
ns
ns
ns
ns
ns
50 ns
100 ns
200 ns
Table 5. Logic Levels
VIH VIL
RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
2.0 V min
0.8 V max
VOH
DATA OUT
2.7 V min
VOL
DATA OUT
0.5 V max
IIH
RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
20 µA max
IIL
RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
−400 µA min
IOH
DATA OUT
−400 µA max
IOL
DATA OUT
3.0 mA min
1
CLK
0
1
D0–D3
A0–A2
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
t2
t1 t3
t4
Figure 3. Timing Diagram, Parallel Mode
t5 t6
Rev. C | Page 6 of 25

6 Page









AD8114 pdf, datenblatt
AD8114/AD8115
0
–10 RL = 1k
RT = 37.5
–20
–30
–40
–50 ALL HOSTILE
–60
–70 ADJACENT
–80
–90
–100
0.1
1 10 100
FREQUENCY (MHz)
Figure 13. AD8114 Crosstalk vs. Frequency
1000
0
–10 VO = 2V p-p
RL = 150
–20
–30
–40
–50
–60 2ND HARMONIC
–70
–80 3RD HARMONIC
–90
–100
1
10
FUNDAMENTAL FREQUENCY (MHz)
Figure 14. AD8114 Distortion vs. Frequency
50
VO = 2V STEP
RL = 150
Data Sheet
0
–10 RL = 1k
RT = 37.5
–20
–30
–40
ALL HOSTILE
–50
ADJACENT
–60
–70
–80
–90
–100
0.1
1 10 100
FREQUENCY (MHz)
Figure 16. AD8115 Crosstalk vs. Frequency
1000
0
–10 VO = 2V p-p
RL = 150
–20
–30
–40
–50
–60 2ND HARMONIC
–70
3RD HARMONIC
–80
–90
–100
1
10
FUNDAMENTAL FREQUENCY (MHz)
Figure 17. AD8115 Distortion vs. Frequency
50
VO = 2V STEP
RL = 150
0 5 10 15 20 25 30 35 40 45
5ns/DIV
Figure 15. AD8114 Settling Time
0 5 10 15 20 25 30 35 40 45
5ns/DIV
Figure 18. AD8115 Settling Time
Rev. C | Page 12 of 25

12 Page





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