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AD8111 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8111
Beschreibung 16 x 8 Buffered Video Crosspoint Switches
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 21 Seiten
AD8111 Datasheet, Funktion
a
260 MHz, 16 ؋ 8 Buffered
Video Crosspoint Switches
AD8110/AD8111
FEATURES
16 ؋ 8 High-Speed Nonblocking Switch Arrays
AD8110: G = +1
AD8111: G = +2
Serial or Parallel Switch Array Control
Serial Data Out Allows “Daisy Chaining” of Multiple
Crosspoints to Create Larger Switch Arrays
Pin-Compatible with AD8108/AD8109 8 ؋ 8 Switch
Arrays
For a 16 ؋ 16 Array See AD8116
Complete Solution
Buffered Inputs
Eight Output Amplifiers, AD8110 (G = +1),
AD8111 (G = +2)
Drives 150 V Loads
Excellent Video Performance
60 MHz 0.1 dB Gain Flatness
0.02% Differential Gain Error (RL = 150 V)
0.028 Differential Phase Error (RL = 150 V)
Excellent AC Performance
260 MHz –3 dB Bandwidth
500 V/ms Slew Rate
Low Power of 50 mA
Low All Hostile Crosstalk of –78 dB @ 5 MHz
Output Disable Allows Direct Connection of Multiple
Device Outputs
Reset Pin Allows Disabling of All Outputs (Connected
Through a Capacitor to Ground Provides “Power-
On” Reset Capability)
Excellent ESD Rating: Exceeds 4000 V Human Body
Model
80-Lead LQFP Package (12 mm ؋ 12 mm)
APPLICATIONS
Routing of High-Speed Signals Including:
Composite Video (NTSC, PAL, S, SECAM)
Component Video (YUV, RGB)
Compressed Video (MPEG, Wavelet)
3-Level Digital Video (HDB3)
PRODUCT DESCRIPTION
The AD8110 and AD8111 are high-speed 16 × 8 video cross-
point switch matrices. They offer a –3 dB signal bandwidth
greater than 260 MHz, and channel switch times of less than
25 ns with 1% settling. With –78 dB of crosstalk and –97 dB
isolation (@ 5 MHz), the AD8110/AD8111 are useful in many
high-speed applications. The differential gain and differential
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3 D4
CLK
DATA IN
UPDATE
CE
RESET
A0
A1
A2
40-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL LOADING
40
PARALLEL LATCH
40
DECODE
8 ؋ 5:16 DECODERS
SET INDIVIDUAL
OR RESET ALL
OUTPUTS
TO "OFF"
8
DATA
OUT
AD8110/AD8111
OUTPUT
128 BUFFER
G = +1,
G = +2
16 INPUTS
SWITCH
MATRIX
8 OUTPUTS
phase of better than 0.02% and 0.02° respectively, along with
0.1 dB flatness out to 60 MHz, make the AD8110/AD8111
ideal for video signal switching.
The AD8110 and AD8111 include eight independent output
buffers that can be placed into a high impedance state for paral-
leling crosspoint outputs so that off channels do not load the
output bus. The AD8110 has a gain of +1, while the AD8111
offers a gain of +2. They operate on voltage supplies of ±5 V
while consuming only 50 mA of idle current. The channel
switching is performed via a serial digital control (which can
accommodate “daisy chaining” of several devices) or via a parallel
control, allowing updating of an individual output without repro-
gramming the entire array.
The AD8110/AD8111 is packaged in an 80-lead LQFP package
and is available over the extended industrial temperature range
of –40°C to +85°C.
Rev. B
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD8111 Datasheet, Funktion
AD8110/AD8111
CE UPDATE CLK
1X
01
X
f
01
00
XX
f
X
X
DATA IN
X
Data i
D0 . . . D4,
A0 . . . A2
X
X
Table III. Operation Truth Table
SER/
DATA OUT RESET PAR Operation/Comment
X
Data i-40
X
1
NA in Parallel 1
Mode
X1
X0
X No change in logic.
0 The data on the serial DATA IN line is loaded
into serial register. The first bit clocked into
the serial register appears at DATA OUT 40
clocks later.
1 The data on the parallel data lines, D0–D4, are
loaded into the 40-bit serial shift register loca-
tion addressed by A0–A2.
X Data in the 40-bit shift register transfers into the
parallel latches that control the switch array.
Latches are transparent.
X Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
PARALLEL
DATA
(OUTPUT
ENABLE)
SER/PAR
D0
D1
D2
D3
D4
DATA IN
(SERIAL)
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0
CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
DATA
OUT
CLK
CE
UPDATE
OUT0 EN
OUT1 EN
OUT2 EN
A0 OUT3 EN
A1 OUT4 EN
A2 OUT5 EN
OUT6 EN
OUT7 EN
RESET
(OUTPUT ENABLE)
LE D
OUT0
B0
Q
LE D
OUT0
B1
Q
LE D
OUT0
B2
Q
LE D
OUT0
B3
Q
LE D
OUT0
EN
CLR Q
LE D
OUT1
B0
Q
LE D
OUT6
EN
CLR Q
LE D
OUT7
B0
Q
LE D
OUT7
B1
Q
LE D
OUT7
B2
Q
LE D
OUT7
B3
Q
LE D
OUT7
EN
CLR Q
DECODE
128
SWITCH MATRIX
Figure 4. Logic Diagram
8
OUTPUT ENABLE
–6– 3&7#

6 Page









AD8111 pdf, datenblatt
AD8110/AD8111
–30
RL = 150
–40
–50
–60
–70
–80
10k
100k
1M
FREQUENCY – Hz
10M
TPC 19. AD8111 PSRR vs. Frequency
100
56.3
31.6
17.8
10
5.63
3.16
10 100 1k 10k 100k 1M 10M
FREQUENCY ؊ Hz
TPC 20. AD8111 Voltage Noise vs. Frequency
100k
10k
1k
100
10
0.1
1 10
FREQUENCY ؊ MHz
100
500
TPC 21. AD8111 Output Impedance, Disabled
5 SWITCHING BETWEEN
TWO INPUTS
4
3
2 UPDATE INPUT
1
0
10
0
TYPICAL VIDEO OUT (RTO)
–10
50ns/DIV
TPC 22. AD8111 Switching Transient (Glitch)
–40
V` OUT = 2V p-p
–50 RL = 150
–60
–70
–80
–90
–100
–110
–120
–130
100k
1M 10M
FREQUENCY – Hz
100M
500M
TPC 23. AD8111 Off Isolation, Input-Output
1k
100
10
1
0.1
100k
1M 10M
FREQUENCY ؊ Hz
100M
500M
TPC 24. AD8111 Output Impedance, Enabled
–12–
3&7#

12 Page





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