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AD9522-0 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9522-0
Beschreibung 12 LVDS/24 CMOS Output Clock Generator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9522-0 Datasheet, Funktion
Data Sheet
12 LVDS/24 CMOS Output Clock Generator
with Integrated 2.8 GHz VCO
AD9522-0
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip voltage controlled oscillator (VCO) tunes from
2.53 GHz to 2.95 GHz
Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
Accepts CMOS, LVPECL, or LVDS references to 250 MHz
Accepts 16.62 MHz to 33.3 MHz crystal for reference input
Optional reference clock doubler
Reference monitoring capability
Revertive automatic and manual reference switchover/
holdover modes
Glitch-free switchover between references
Automatic recovery from holdover
Digital or analog lock detect, selectable
Optional zero delay operation
Twelve 800 MHz LVDS outputs divided into 4 groups
Each group of 3 has a 1-to-32 divider with phase delay
Additive output jitter as low as 242 fs rms
Channel-to-channel skew grouped outputs < 60 ps
Each LVDS output can be configured as 2 CMOS outputs
(for fOUT ≤ 250 MHz)
Automatic synchronization of all outputs on power-up
Manual synchronization of outputs as needed
SPI- and I²C-compatible serial control port
64-lead LFCSP
Nonvolatile EEPROM stores configuration settings
APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
GENERAL DESCRIPTION
The AD9522-01 provides a multioutput clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 2.53 GHz
to 2.95 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz
can also be used.
FUNCTIONAL BLOCK DIAGRAM
CP LF
OPTIONAL
REFIN
REFIN
REF1
REF2
STATUS
MONITOR
VCO
CLK
DIVIDER
AND MUXES
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
ZERO
DELAY
LVDS/
CMOS
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
SPI/I2C CONTROL
PORT AND
EEPROM
DIGITAL LOGIC
AD9522
Figure 1.
The AD9522 serial interface supports both SPI and I²C® ports.
An in-package EEPROM can be programmed through the
serial interface and store user-defined register settings for
power-up and chip reset.
The AD9522 features 12 LVDS outputs in four groups. Any of
the 800 MHz LVDS outputs can be reconfigured as two
250 MHz CMOS outputs.
Each group of outputs has a divider that allows both the divide
ratio (from 1 to 32) and the phase (coarse delay) to be set.
The AD9522 is available in a 64-lead LFCSP and can be operated
from a single 3.3 V supply. The external VCO can have an
operating voltage up to 5.5 V.
The AD9522 is specified for operation over the standard industrial
range of −40°C to +85°C.
The AD9520-0 is an equivalent part to the AD9522-0 featuring
LVPECL/CMOS drivers instead of LVDS/CMOS drivers.
1 The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-0 is used, it is referring to that specific
member of the AD9522 family.
Rev. A
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Tel: 781.329.4700 ©2008–2015 Analog Devices, Inc. All rights reserved.
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AD9522-0 Datasheet, Funktion
Data Sheet
AD9522-0
SPECIFICATIONS
Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum
(min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
VS
VCP
RSET Pin Resistor
CPRSET Pin Resistor
BYPASS Pin Capacitor
Min Typ Max Unit Test Conditions/Comments
3.135 3.3 3.465 V
3.3 V ± 5%
VS
5.25 V
This supply is usually at the same voltage as VS; set VCP = 5.0 V ± 5% only if
connecting a 5 V external VCO/VCXO
4.12 kΩ Sets internal biasing currents; connect to ground
5.1 kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA);
actual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground
220 nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
Frequency Range
VCO Gain (KVCO)
Tuning Voltage (VT)
Frequency Pushing (Open-Loop)
Phase Noise at 1 kHz Offset
Phase Noise at 100 kHz Offset
Phase Noise at 1 MHz Offset
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled)
with DC Offset Off )
Input Frequency (AC-Coupled
with DC Offset On)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled
with DC Offset Off )
Input Sensitivity (AC-Coupled
with DC Offset On)
Input Logic High, DC Offset Off
Input Logic Low, DC Offset Off
Input Current
Input Capacitance
Pulse Width High/Low
Min Typ Max Unit Test Conditions/Comments
2530
0.5
52
1
−60
−118
−135
2950
VCP −
0.5
MHz
MHz/V
V
MHz/V
dBc/Hz
dBc/Hz
dBc/Hz
See Figure 8
VCP ≤ VS when using internal VCO
LVDS output; fVCO = 2750 MHz; fOUT = 685MHz
LVDS output; fVCO = 2750 MHz; fOUT = 685MHz
LVDS output; fVCO = 2750 MHz; fOUT = 685MHz
Differential mode (can accommodate single-ended
input by ac grounding the unused complementary input)
0 250 MHz Frequencies below about 1 MHz must be dc-coupled;
be careful to match VCM (self-bias voltage)
280 mV p-p PLL figure of merit (FOM) increases with increasing
slew rate (see Figure 12); the input sensitivity is
sufficient for ac-coupled LVDS and LVPECL signals
1.35 1.60 1.75 V
Self-bias voltage of REFIN1
1.30 1.50 1.60 V
Self-bias voltage of REFIN1
4.0 4.8 5.9 kΩ
Self-biased1
4.4 5.3 6.4 kΩ
Self-biased1
Two single-ended CMOS-compatible inputs
10 250 MHz Slew rate must be > 50 V/µs
250 MHz
Slew rate must be > 50 V/µs, and input amplitude
sensitivity specification must be met; see input sensitivity
0 250 MHz Slew rate > 50 V/µs; CMOS levels
0.55 3.28 V p-p VIH must not exceed VS
1.5 2.78 V p-p VIH must not exceed VS
2.0
−100
1.8
2
0.8
+100
V
V
µA
pF
ns
Rev. A | Page 5 of 84
Each pin, REFIN (REF1)/REFIN (REF2)
Amount of time a square wave is high/low determines the
allowable input duty cycle

6 Page









AD9522-0 pdf, datenblatt
Data Sheet
AD9522-0
CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter
LVDS ABSOLUTE PHASE NOISE
VCO = 2950 MHz; Output = 737.5 MHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
VCO = 2750 MHz; Output = 685 MHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
VCO = 2550 MHz; Output = 632.5 MHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
Min Typ Max Unit
Test Conditions/Comments
Internal VCO; VCO divider = 4; LVDS output and for loop
bandwidths < 1 kHz
−59
−90
−115
−133
−146
−149
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−60
−92
−118
−135
−148
−151
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−64
−95
−120
−137
−148
−151
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVDS OUTPUT ABSOLUTE TIME JITTER
VCO = 2949 MHz; LVDS = 245.76 MHz; PLL LBW = 55 kHz
VCO = 2580 MHz; LVDS = 122.88 MHz; PLL LBW = 55 kHz
VCO = 2580 MHz; LVDS = 61.44 MHz; PLL LBW = 55 kHz
Min Typ Max Unit Test Conditions/Comments
Application example based on a typical
setup where the reference source is
clean, so a wider PLL loop bandwidth is
used; reference = 15.36 MHz; R DIV = 1
187 fs rms Integration bandwidth = 200 kHz to 10 MHz
352 fs rms Integration bandwidth = 12 kHz to 20 MHz
166 fs rms Integration bandwidth = 200 kHz to 10 MHz
321 fs rms Integration bandwidth = 12 kHz to 20 MHz
218 fs rms Integration bandwidth = 200 kHz to 10 MHz
378 fs rms Integration bandwidth = 12 kHz to 20 MHz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVDS OUTPUT ABSOLUTE TIME JITTER
VCO = 2799 MHz; LVDS = 155.52 MHz; PLL LBW = 1.8 kHz
VCO = 2580 MHz; LVDS = 122.88 MHz; PLL LBW = 1.8 kHz
Min Typ Max Unit Test Conditions/Comments
Application example based on a typical
setup where the reference source is jittery,
so a narrower PLL loop bandwidth is used;
reference = 19.44 MHz; R DIV = 162
617 fs rms Integration bandwidth = 12 kHz to 20 MHz
514 fs rms Integration bandwidth = 12 kHz to 20 MHz
Rev. A | Page 11 of 84

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