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AD9520-3 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9520-3
Beschreibung 12 LVPECL/24 CMOS Output Clock Generator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9520-3 Datasheet, Funktion
Data Sheet
12 LVPECL/24 CMOS Output Clock
Generator with Integrated 2 GHz VCO
AD9520-3
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 1.72 GHz to 2.25 GHz
Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
Accepts CMOS, LVDS, or LVPECL references to 250 MHz
Accepts 16.62 MHz to 33.3 MHz crystal for reference input
Optional reference clock doubler
Reference monitoring capability
Automatic/manual reference holdover and reference
switchover modes, with revertive switching
Glitch-free switchover between references
Automatic recovery from holdover
Digital or analog lock detect, selectable
Optional zero delay operation
Twelve 1.6 GHz LVPECL outputs divided into 4 groups
Each group of 3 outputs shares a 1-to-32 divider with
phase delay
Additive output jitter as low as 225 fs rms
Channel-to-channel skew grouped outputs < 16 ps
Each LVPECL output can be configured as 2 CMOS outputs
(for fOUT ≤ 250 MHz)
Automatic synchronization of all outputs on power-up
Manual output synchronization available
SPI- and I²C-compatible serial control port
64-lead LFCSP
Nonvolatile EEPROM stores configuration settings
APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10GFC,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
GENERAL DESCRIPTION
The AD9520-31 provides a multioutput clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 1.72 GHz
to 2.25 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz
can also be used.
FUNCTIONAL BLOCK DIAGRAM
CP LF
OPTIONAL
REFIN
REFIN
CLK
REF1
REF2
STATUS
MONITOR
VCO
DIVIDER
AND MUXES
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
ZERO
DELAY
LVPECL/
CMOS
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
SPI/I2C CONTROL
PORT AND
EEPROM
DIGITAL LOGIC
AD9520
Figure 1.
The AD9520-3 serial interface supports both SPI and I²C ports.
An in-package EEPROM, which can be programmed through the
serial interface, can store user-defined register settings for
power-up and chip reset.
The features 12 LVPECL outputs in four groups. Any of the 1.6
GHz LVPECL outputs can be reconfigured as two 250 MHz
CMOS outputs. If an application requires LVDS drivers instead
of LVPECL drivers, refer to the AD9522-3.
Each group of three outputs has a divider that allows both the
divide ratio (from 1 to 32) and the phase offset or coarse time
delay to be set.
The is available in a 64-lead LFCSP and can be operated from a
single 3.3 V supply. The external VCO can have an operating
voltage of up to 5.5 V. A separate output driver power supply
can be from 2.375 V to 3.465 V.
The AD9520-3 is specified for operation over the standard
industrial range of −40°C to +85°C.
1 AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-3 is used, it refers to that specific member of the
AD9520 family.
Rev. B
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Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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AD9520-3 Datasheet, Funktion
AD9520-3
Data Sheet
Parameter
PHASE OFFSET IN ZERO DELAY
Phase Offset (REF-to-LVPECL Clock Output
Pins) in Internal Zero Delay Mode
Phase Offset (REF-to-LVPECL Clock Output
Pins) in Internal Zero Delay Mode
Phase Offset (REF-to-CLK Input Pins) in
External Zero Delay Mode
Phase Offset (REF-to-CLK Input Pins) in
External Zero Delay Mode
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge Pump/
Phase Frequency Detector 2
Min
560
−320
140
−460
Typ Max
1060
+50
630
−20
1310
+240
870
+200
500 kHz PFD Frequency
1 MHz PFD Frequency
10 MHz PFD Frequency
50 MHz PFD Frequency
PLL Figure of Merit (FOM)
−165
−162
−152
−144
−222
PLL DIGITAL LOCK DETECT WINDOW3
Lock Threshold (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Unlock Threshold (Hysteresis)3
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
3.5
7.5
3.5
7
15
11
Unit Test Conditions/Comments
REF refers to REFIN (REF1)/REFIN (REF2)
ps When N delay and R delay are bypassed
ps When N delay setting = 110b, and R delay is bypassed
ps When N delay and R delay are bypassed
ps When N delay setting = 011b, and R delay is bypassed
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ns
ns
ns
ns
ns
ns
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output of the
VCO and subtracting 20 log(N) (where N is the value of
the N divider).
Reference slew rate > 0.5 V/ns; FOM + 10 log(fPFD) is an
approximation of the PFD/CP in-band phase noise (in the
flat region) inside the PLL loop bandwidth; when
running closed-loop, the phase noise, as observed at the
VCO output, is increased by 20 log(N); PLL figure of merit
decreases with decreasing slew rate; see Figure 12
Signal available at the LD, STATUS, and REFMON pins
when selected by appropriate register settings; the lock
detect threshold varies linearly with the value of the
CPRSET resistor
Selected by Register 0x017[1:0] and Register 0x018[4]
(this is the threshold to go from unlock to lock)
Register 0x017[1:0] = 00b, 01b,11b;
Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
Selected by Register 0x017[1:0] and Register 0x018[4] (this
is the threshold to go from lock to unlock)
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
1 The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
2 In-band means within the LBW of the PLL.
3 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. B | Page 6 of 80

6 Page









AD9520-3 pdf, datenblatt
AD9520-3
Data Sheet
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
Min Typ Max Unit Test Conditions/Comments
Application example based on a typical setup
using an external 245.76 MHz VCXO (Toyocom
TCO-2112); reference = 15.36 MHz; R divider = 1
54 fs rms Integration BW = 200 kHz to 5 MHz
77 fs rms Integration BW = 200 kHz to 10 MHz
109 fs rms Integration BW = 12 kHz to 20 MHz
79 fs rms Integration BW = 200 kHz to 5 MHz
114 fs rms Integration BW = 200 kHz to 10 MHz
163 fs rms Integration BW = 12 kHz to 20 MHz
124 fs rms Integration BW = 200 kHz to 5 MHz
176 fs rms Integration BW = 200 kHz to 10 MHz
259 fs rms Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK = 622.08 MHz
Any LVPECL Output = 622.08 MHz
Divide Ratio = 1
CLK = 622.08 MHz
Any LVPECL Output = 155.52 MHz
Divide Ratio = 4
CLK = 1000 MHz
Any LVPECL Output = 100 MHz
Divide Ratio = 10
CLK = 500 MHz
Any LVPECL Output = 100 MHz
Divide Ratio = 5
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 200 MHz
Any CMOS Output Pair = 100 MHz
Divide Ratio = 2
Min Typ Max Unit Test Conditions/Comments
Distribution section only; does not include PLL
and VCO; measured at rising edge of clock
signal
46 fs rms Integration bandwidth = 12 kHz to 20 MHz
64 fs rms Integration bandwidth = 12 kHz to 20 MHz
223 fs rms Calculated from SNR of ADC method
Broadband jitter
209 fs rms Calculated from SNR of ADC method
Broadband jitter
Distribution section only; does not include PLL
and VCO
325 fs rms Calculated from SNR of ADC method
Broadband jitter
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
Min
CLK = 1.0 GHz; VCO DIV = 5; LVPECL = 100 MHz;
Channel Divider = 2; Duty-Cycle Correction = Off
CLK = 500 MHz; VCO DIV = 5; LVPECL = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = On
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = Off
CLK = 1600 MHz; VCO DIV = 2; CMOS = 100 MHz;
Channel Divider = 8; Duty-Cycle Correction = Off
Typ Max Unit Test Conditions/Comments
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
230 fs rms Calculated from SNR of ADC method
(broadband jitter)
215 fs rms Calculated from SNR of ADC method
(broadband jitter)
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
326 fs rms Calculated from SNR of ADC method
(broadband jitter)
362 fs rms Calculated from SNR of ADC method
(broadband jitter)
Rev. B | Page 12 of 80

12 Page





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