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PDF AD9516-2 Data sheet ( Hoja de datos )
| Número de pieza | AD9516-2 | |
| Descripción | 14-Output Clock Generator | |
| Fabricantes | Analog Devices | |
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Data Sheet
14-Output Clock Generator with
Integrated 2.2 GHz VCO
AD9516-2
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.05 GHz to 2.33 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
6 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
4 pairs of 800 MHz LVDS clock outputs
Each output pair shares two cascaded 1-to-32 dividers
with coarse phase delay
Additive output jitter: 275 fs rms
Fine delay adjust (Δt) on each LVDS output
Each LVDS output can be reconfigured as two 250 MHz
CMOS outputs
Automatic synchronization of all outputs on power-up
Manual output synchronization available
64-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
GENERAL DESCRIPTION
The AD9516-21 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an on-
chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz to
2.33 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz
can be used.
The AD9516-2 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
FUNCTIONAL BLOCK DIAGRAM
CP LF
REFIN
REF1
REF2
STATUS
MONITOR
VCO
CLK
DIVIDER
AND MUXs
DIV/Φ
LVPECL
DIV/Φ
LVPECL
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
LVPECL
Δt
Δt
LVDS/CMOS
Δt
Δt
LVDS/CMOS
SERIAL CONTROL PORT
AND
DIGITAL LOGIC
AD9516-2
Figure 1.
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
The AD9516-2 features six LVPECL outputs (in three pairs)
and four LVDS outputs (in two pairs). Each LVDS output can
be reconfigured as two CMOS outputs. The LVPECL outputs
operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and
the CMOS outputs operate to 250 MHz.
Each pair of outputs has dividers that allow both the divide
ratio and coarse delay (or phase) to be set. The range of division
for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs
allow a range of divisions up to a maximum of 1024.
The AD9516-0 is available in a 64-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5 V. A separate
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9516-2 is specified for operation over the standard
industrial range of −40°C to +85°C.
1 AD9516 is used throughout to refer to all the members of the AD9516 family.
However, when AD9516-2 is used, it refers to that specific member of the
AD9516 family.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD9516-2
Parameter
CHARGE PUMP (CP)
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
CPRSET Range
ICP High Impedance Mode Leakage
Sink-and-Source Current Matching
ICP vs. CPV
ICP vs. Temperature
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
Min
PLL DIVIDER DELAYS
000
001
010
011
100
101
110
111
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Is Within the LBW of the PLL)
At 500 kHz PFD Frequency
At 1 MHz PFD Frequency
At 10 MHz PFD Frequency
At 50 MHz PFD Frequency
PLL Figure of Merit (FOM)
PLL DIGITAL LOCK DETECT WINDOW2
Required to Lock (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
To Unlock After Lock (Hysteresis)2
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Typ Max
4.8
0.60
2.5
2.7/10
1
2
1.5
2
300
600
900
200
1000
2400
3000
3000
300
Off
330
440
550
660
770
880
990
−165
−162
−151
−143
−220
3.5
7.5
3.5
7
15
11
Unit Test Conditions/Comments
Programmable
mA With CPRSET = 5.1 kΩ
mA
% CPV = VCP/2
kΩ
nA
% 0.5 < CPV < VCP − 0.5 V
% 0.5 < CPV < VCP − 0.5 V
% CPV = VCP/2
See the VCXO/VCO Feedback Divider N—P, A, B, R section
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz A, B counter input frequency (prescaler input frequency divided
by P)
Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see Table 54
ps
ps
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ns
ns
ns
The PLL in-band phase noise floor is estimated by measuring the
in-band phase noise at the output of the VCO and subtracting
20log(N) (where N is the value of the N divider)
Reference slew rate > 0.25 V/ns; FOM + 10log (fPFD) is an approxi-
mation of the PFD/CP in-band phase noise (in the flat region)
inside the PLL loop bandwidth; when running closed loop, the
phase noise, as observed at the VCO output, is increased by 20log(N)
Signal available at LD, STATUS, and REFMON pins when selected
by appropriate register settings
Selected by Register 0x017[1:0] and Register 0x018[4]
Register 0x017[1:0] = 00b, 01b,11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
1 REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
2 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. C | Page 5 of 80
5 Page 
Data Sheet
AD9516-2
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
Min
CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1
CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5
LVDS OUTPUT ADDITIVE TIME JITTER
CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2;
VCO Divider Not Used
CLK = 1 GHz; LVDS = 200 MHz; Divider = 5
CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16
Typ Max Unit Test Conditions/Comments
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
40 fs rms BW = 12 kHz to 20 MHz
80 fs rms BW = 12 kHz to 20 MHz
215 fs rms Calculated from SNR of ADC method;
DCC not used for even divides
245 fs rms Calculated from SNR of ADC method; DCC on
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
85 fs rms BW = 12 kHz to 20 MHz
113 fs rms BW = 12 kHz to 20 MHz
280 fs rms Calculated from SNR of ADC method;
DCC not used for even divides
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
365 fs rms Calculated from SNR of ADC method;
DCC not used for even divides
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
Min Typ Max
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
LVDS OUTPUT ADDITIVE TIME JITTER
210
CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
CMOS OUTPUT ADDITIVE TIME JITTER
285
CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
350
Unit
fs rms
Test Conditions/Comments
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method
fs rms
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method
fs rms
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method
Rev. C | Page 11 of 80
11 Page | ||
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| PDF Descargar | [ Datasheet AD9516-2.PDF ] | |
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