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AD9245 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9245
Beschreibung 3V A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9245 Datasheet, Funktion
Data Sheet
14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
3 V A/D Converter
AD9245
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 72.7 dBc to Nyquist
SFDR = 83.0 dBc to Nyquist
Low power
366 mW at 80 MSPS
300 mW at 65 MSPS
165 mW at 40 MSPS
90 mW at 20 MSPS
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = ±0.5 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty-cycle stabilizer
APPLICATIONS
Medical imaging equipment
IF sampling in communications receivers
WCDMA, CDMA-One, CDMA-2000, and TDS-CDMA
Battery-powered instruments
Hand-held scopemeters
Spectrum analyzers
Power-sensitive military applications
GENERAL DESCRIPTION
The AD9245 is a monolithic, single 3 V supply, 14-bit,
20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital
converter (ADC) featuring a high performance sample-and-
hold amplifier (SHA) and voltage reference. The AD9245 uses a
multistage differential pipelined architecture with output error
correction logic to provide 14-bit accuracy and guarantee no
missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9245 is
suitable for applications in communications, imaging, and
medical ultrasound.
VIN+
VIN–
REFT
REFB
VREF
SENSE
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
AD9245
SHA
MDAC1
8-STAGE
1 1/2-BIT PIPELINE
A/D
4
A/D
16
3
REF
SELECT
CORRECTION LOGIC
14
OUTPUT BUFFERS
0.5V
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
OTR
D13 (MSB)
D0 (LSB)
AGND
CLK PDWN MODE DGND
Figure 1.
A single-ended clock input is used to control all internal con-
version cycles. A duty cycle stabilizer (DCS) compensates for
wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9245 is available in a 32-lead LFCSP and is specified over
the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9245 operates from a single 3 V power supply and
features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.
2. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
3. The AD9245 is pin-compatible with the AD9215, AD9235,
and AD9236. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.
4. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
5. The OTR output bit indicates when the signal is beyond the
selected input range.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD9245 Datasheet, Funktion
Data Sheet
AD9245
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, DCS off,
unless otherwise noted.
Table 3.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
WORST HARMONIC (SECOND OR THIRD)
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
AD9245BCP-20
AD9245BCP-40
AD9245BCP-65
Min Typ Max Min Typ Max Min Typ Max Unit
73.5
70.6 73.3
70.8
73.5
70.5 73.4
71.3
73.1
70.3 72.7
70.2
dBc
dBc
dBc
dBc
dBc
73.4
69.4 73.2
69.5
73.4
70.0 73.2
69.1
73.0
68.4 72.6
67.9
dBc
dBc
dBc
dBc
dBc
11.9 Bits
11.8 Bits
11.7 Bits
–89 –80
–89 –80
dBc
dBc
–83 –74 dBc
92.0
80.0 89.0
84.0
92.0
80.0 89.0
85.0
92.0
74.0 83.0
80.5
dBc
dBc
dBc
dBc
dBc
Rev. E | Page 5 of 32

6 Page









AD9245 pdf, datenblatt
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9245
DNC 1
CLK 2
DNC 3
PDWN 4
(LSB) D0 5
D1 6
D2 7
D3 8
AD9245
TOP VIEW
(Not to Scale)
24 VREF
23 SENSE
22 MODE
21 OTR
20 D13 (MSB)
19 D12
18 D11
17 D10
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. IT IS RECOMMENDED THAT THE EXPOSED PADDLE BE SOLDERED TO THE GROUND PLANE
FOR THE LFCSP PACKAGE. THERE IS AN INCREASED RELIABILITY OF THE SOLDER JOINTS,
AND THE MAXIMUM THERMAL CAPABILITY OF THE PACKAGE IS ACHIEVED WITH THE
EXPOSED PADDLE SOLDERED TO THE CUSTOMER BOARD.
Figure 3. LFCSP Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
1, 3 DNC
2 CLK
4 PDWN
5 to 14, 17 to 20
D0 (LSB) to D13 (MSB)
15 DGND
16 DRVDD
21 OTR
22 MODE
23 SENSE
24 VREF
25 REFB
26 REFT
27, 32
AVDD
28, 31
AGND
29 VIN+
30 VIN–
EPAD
Description
Do Not Connect
Clock Input Pin
Power-Down Function Select
Data Output Bits
Digital Output Ground
Digital Output Driver Supply
Out-of-Range Indicator
Data Format Select and DCS Mode Selection (See Table 11)
Reference Mode Selection (See Table 10)
Voltage Reference Input/Output
Differential Reference (–)
Differential Reference (+)
Analog Power Supply
Analog Ground
Analog Input Pin (+)
Analog Input Pin (–)
Exposed Pad. It is recommended that the exposed paddle be soldered to the ground
plane for the LFCSP package. There is an increased reliability of the solder joints, and
the maximum thermal capability of the package is achieved with the exposed paddle
soldered to the customer board.
Rev. E | Page 11 of 32

12 Page





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