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AD9235 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9235
Beschreibung 3V A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9235 Datasheet, Funktion
Data Sheet
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70 dBc to Nyquist at 65 MSPS
SFDR = 85 dBc to Nyquist at 65 MSPS
Low power: 300 mW at 65 MSPS
Differential input with 500 MHz bandwidth
On-chip reference and SHA
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
IS-95, CDMA-One, IMT-2000
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
GENERAL DESCRIPTION
The AD9235 is a family of monolithic, single 3 V supply, 12-bit,
20/40/65 MSPS analog-to-digital converters (ADCs). This
family features a high performance sample-and-hold amplifier
(SHA) and voltage reference. The AD9235 uses a multistage
differential pipelined architecture with output error correction
logic to provide 12-bit accuracy at 20/40/65 MSPS data rates
and guarantee no missing codes over the full operating
temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9235 is suitable for applications in communica-
tions, imaging, and medical ultrasound.
A single-ended clock input is used to control all internal
conversion cycles. A duty cycle stabilizer (DCS) compensates
for wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
12-Bit, 20/40/65 MSPS
3 V A/D Converter
AD9235
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
VIN+
VIN–
REFT
REFB
SHA
VREF
SENSE
REF
SELECT
MDAC1
4
A/D
8-STAGE
1 1/2-BIT
PIPELINE
16
A/D
3
CORRECTION LOGIC
12
OUTPUT BUFFERS
AD9235
CLOCK
DUTY CYCLE
STABILIZER
0.5V
MODE
SELECT
OTR
D11
D0
AGND
CLK
PDWN MODE DGND
Figure 1.
can be used with the most significant bit to determine low or
high overflow.
Fabricated on an advanced CMOS process, the AD9235 is avail-
able in a 28-lead TSSOP and a 32-lead LFCSP and is specified
over the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9235 operates from a single 3 V power supply and
features a separate digital output driver supply to accommo-
date 2.5 V and 3.3 V logic families.
2. Operating at 65 MSPS, the AD9235 consumes a low 300 mW.
3. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
4. The AD9235 pinout is similar to the AD9214-65, a 10-bit,
65 MSPS ADC. This allows a simplified upgrade path from
10 bits to 12 bits for 65 MSPS systems.
5. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
6. The OTR output bit indicates when the signal is beyond the
selected input range.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no re-
sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.






AD9235 Datasheet, Funktion
Data Sheet
AD9235
ANALOG
INPUT
N
N+1
N+2
N+8
N–1 N+3
tA N+4 N+7
N+5 N+6
CLK
DATA
OUT
N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1
tPD = 6.0ns MAX
2.0ns MIN
N
Figure 2. Timing Diagram
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, AIN = –0.5 dBFS, 1.0 V internal reference, TMIN to TMAX,
unless otherwise noted.
Table 4.
Parameter
SIGNAL-TO-NOISE RATIO
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
SIGNAL-TO-NOISE RATIO
AND DISTORTION
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
TOTAL HARMONIC DISTORTION
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
WORST HARMONIC
(SECOND OR THIRD)
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65
Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit
25°C V
Full IV
25°C I
Full IV
25°C I
Full IV
25°C I
25°C V
70.8
70.0 70.4
70.6
68.7
70.6
69.9 70.3
70.4
68.5
70.5
68.7 69.7
70.1
68.3
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
25°C V
Full IV
25°C I
Full IV
25°C I
Full IV
25°C I
25°C V
25°C V
Full IV
25°C I
Full IV
25°C I
Full IV
25°C I
25°C V
70.6
69.9 70.3
70.5
68.6
70.5
69.7 70.2
70.3
68.3
70.4
68.3 69.5
69.9
67.8
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
–88.0
–86.0
–87.4
–79.0
–84.0
–89.0
–85.5 –79.0
–86.0
–82.5
–87.5
–81.8
–82.0
–78.0
–74.0
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Full IV
Full IV
Full IV
–90.0 –80.0
–90.0 –80.0
–83.5
–74.0
dBc
dBc
dBc
Rev. D | Page 5 of 40

6 Page









AD9235 pdf, datenblatt
Data Sheet
AD9235
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V, fSAMPLE = 65 MSPS with DCS disabled, TA = 25°C, 2 V differential input, AIN = −0.5 dBFS, VREF = 1.0 V,
unless otherwise noted.
0
SNR = 70.3dBc
SINAD = 70.2dBc
–20 ENOB = 11.4 BITS
THD = –86.3dBc
SFDR = 89.9dBc
–40
–60
–80
–100
–120
0
6.5 13.0 19.5 26.0
FREQUENCY (MHz)
Figure 9. Single Tone 8K FFT with fIN = 10 MHz
32.5
100
95 SFDR (2V DIFF)
90
85
80
SNR (2V SE)
75
70
65 SNR (2V DIFF)
60
55 SFDR (2V SE)
50
40
45 50 55 60
SAMPLE RATE (MSPS)
Figure 12. AD9235-65: Single Tone SNR/SFDR vs.
fCLK with fIN = Nyquist (32.5 MHz)
65
0
SNR = 69.4dBc
SINAD = 69.1dBc
–20
ENOB = 11.2 BITS
THD = –81.0dBc
SFDR = 83.8dBc
–40
–60
–80
–100
–120
65.0
71.5 78.0 84.5
FREQUENCY (MHz)
91.0
Figure 10. Single Tone 8K FFT with fIN = 70 MHz
100
95
90
85
SFDR (2V DIFF)
80
SNR (2V SE)
75
SNR (2V DIFF)
70
65
SFDR (2V SE)
60
55
50
20
25 30 35
SAMPLE RATE (MSPS)
40
Figure 13. AD9235-40: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (20 MHz)
0
SNR = 68.5dBc
SINAD = 66.5dBc
ENOB = 10.8 BITS
–20 THD = –71.0dBc
SFDR = 71.2dBc
–40
–60
–80
–100
–120
97.5
104.0
110.5
117.0
FREQUENCY (MHz)
123.5
Figure 11. Single Tone 8K FFT with fIN = 100 MHz
130.0
100
95 SFDR (2V DIFF)
90
85
SFDR (2V SE)
80
75
SNR (2V SE)
70
65
SNR (2V DIFF)
60
55
50
0 5 10 15 20
SAMPLE RATE (MSPS)
Figure 14. AD9235-20: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (10 MHz)
Rev. D | Page 11 of 40

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