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ADF4117 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF4117
Beschreibung RF PLL Frequency Synthesizers
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
ADF4117 Datasheet, Funktion
RF PLL Frequency Synthesizers
ADF4116/ADF4117/ADF4118
FEATURES
GENERAL DESCRIPTION
ADF4116: 550 MHz
ADF4117: 1.2 GHz
ADF4118: 3.0 GHz
2.7 V to 5.5 V power supply
Separate VP allows extended tuning voltage in 3 V systems
Y Grade: −40°C to +125°C
Dual-modulus prescaler
ADF4116: 8/9
ADF4117/ADF4118: 32/33
3-wire serial interface
Digital lock detect
Power-down mode
Fastlock mode
The ADF411x family of frequency synthesizers can be used to
implement local oscillators (LO) in the upconversion and
downconversion sections of wireless receivers and transmitters.
They consist of a low noise digital phase frequency detector
(PFD), a precision charge pump, a programmable reference
divider, programmable A and B counters, and a dual-modulus
prescaler (P/P + 1). The A (5-bit) and B (13-bit) counters, in
conjunction with the dual-modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R counter) allows selectable REFIN frequencies
at the PFD input. A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO).
APPLICATIONS
All of the on-chip registers are controlled via a simple 3-wire
Base stations for wireless radio
(GSM, PCS, DCS, CDMA, WCDMA)
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
Wireless handsets
(GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
Communications test equipment
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP CPGND
ADF4116/ADF4117/ADF4118
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
14-BIT
R COUNTER
14
R COUNTER
LATCH
21-BIT
INPUT REGISTER 19
FUNCTION
LATCH
SDOUT
FROM
FUNCTION LATCH
A, B COUNTER
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P + 1
LOAD
LOAD
5-BIT
A COUNTER
18
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
AVDD
SDOUT
5
CE
AGND
DGND
Figure 1.
CHARGE
PUMP
MUX
HIGH Z
M3 M2 M1
FLO
SWITCH
CP
MUXOUT
FLO
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2007 Analog Devices, Inc. All rights reserved.






ADF4117 Datasheet, Funktion
ADF4116/ADF4117/ADF4118
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to GND1
AVDD to DVDD
VP to GND1
VP to AVDD
Digital I/O Voltage to GND1
Analog I/O Voltage to GND1
REFIN, RFINA, RFINB to GND1
RFINA to RFINB
Operating Temperature Range
Industrial (B Version)
Extended (Y Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Transistor Count
CMOS
Bipolar
Rating
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to +7 V
−0.3 V to +5.5 V
−0.3 V to VDD + 0.3 V
−0.3 V to VP + 0.3 V
−0.3 V to VDD + 0.3 V
±320 mV
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
150°C
112°C/W
260°C
40 sec
6425
303
1 GND = AGND = DGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
Rev. D | Page 6 of 28

6 Page









ADF4117 pdf, datenblatt
ADF4116/ADF4117/ADF4118
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 25. SW1 and SW2
are normally closed switches; SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
POWER-DOWN
CONTROL
NC 100k
REFIN NC
SW2
SW1
SW3
NO
TO R COUNTER
BUFFER
Figure 25. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 26. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
BIAS
GENERATOR
1.6V
500
500
AVDD
RFINA
RFINB
AGND
Figure 26. RF Input Stage
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A counter
and B counter, enables the large division ratio, N, to be realized
(N = PB + A). The dual-modulus prescaler takes the CML clock
from the RF input stage and divides it down to a manageable
frequency for the CMOS A counter and CMOS B counter. The
prescaler is programmable. It can be set in software to 8/9 for the
ADF4116 and to 32/33 for the ADF4117 and ADF4118. It is based
on a synchronous 4/5 core.
A COUNTER AND B COUNTER
The A CMOS counter and B CMOS counter combine with the
dual-modulus prescaler to allow a wide ranging division ratio in
the PLL feedback counter. The counters are specified to work
when the prescaler output is 200 MHz or less.
Pulse Swallow Function
The A counter and B counter, in conjunction with the dual-
modulus prescaler, make it possible to generate output
frequencies that are spaced only by the reference frequency
divided by R. The equation for the VCO frequency is as follows:
fVCO = [(P × B) + A]× fREFIN / R
where:
fVCO is the output frequency of external voltage controlled
oscillator (VCO).
P is the preset modulus of dual-modulus prescaler.
B is the preset divide ratio of binary 13-bit counter (3 to 8191).
A is the preset divide ratio of binary 5-bit swallow counter (0 to 31).
fREFIN is the output frequency of the external reference frequency
oscillator.
R is the preset divide ratio of binary 14-bit programmable
reference counter (1 to 16,383).
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the input clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
N = BP + A
FROM RF
INPUT STAGE
PRESCALER
P/P + 1
MODULUS
CONTROL
13-BIT
B COUNTER
LOAD
LOAD
5-BIT
A COUNTER
TO PFD
Figure 27. A Counter and B Counter
Rev. D | Page 12 of 28

12 Page





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