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ADG1202 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADG1202
Beschreibung iCMOS SPST
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
ADG1202 Datasheet, Funktion
Low Capacitance, Low Charge Injection,
±15 V/+12 V iCMOS SPST in SOT-23
ADG1201/ADG1202
FEATURES
2.4 pF off capacitance
<1 pC charge injection
Low leakage; 0.6 nA maximum @ 85°C
120 Ω on resistance
Fully specified at ±15 V, +12 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
6-lead SOT-23 package
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
GENERAL DESCRIPTION
The ADG1201/ADG1202 are monolithic complementary
metal-oxide semiconductor (CMOS) devices containing
an SPST switch designed in an iCMOS® (industrial CMOS)
process. iCMOS is a modular manufacturing process
combining high voltage CMOS and bipolar technologies.
It enables the development of a wide range of high perform-
ance analog ICs capable of 33 V operation in a footprint
that no previous generation of high voltage parts has been
able to achieve. Unlike analog ICs using conventional
CMOS processes, iCMOS components can tolerate high
supply voltages while providing increased performance,
dramatically lower power consumption, and reduced
package size.
The ultralow capacitance and charge injection of these
switches make them ideal solutions for data acquisition
and sample-and-hold applications, where low glitch and fast
settling are required. Fast switching speed coupled with
high signal bandwidth make the parts suitable for video
signal switching.
FUNCTIONAL BLOCK DIAGRAM
ADG1201
ADG1202
S DS D
IN IN
SWITCHES SHOWN FOR A LOGIC “1” INPUT
Figure 1.
iCMOS construction ensures ultralow power dissipation,
making the parts ideally suited for portable and battery-
powered instruments.
The ADG1201/ADG1202 contain a single-pole/single-throw
(SPST) switch. Figure 1 shows that with a logic input of 1, the
switch of the ADG1201 is closed and that of the ADG1202 is
open. Each switch conducts equally well in both directions when
on and has an input signal range that extends to the supplies. In
the off condition, signal levels up to the supplies are blocked.
PRODUCT HIGHLIGHTS
1. Ultralow capacitance.
2. <1 pC charge injection.
3. Ultralow leakage.
4. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
5. No VL logic power supply required.
6. SOT-23 package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.






ADG1202 Datasheet, Funktion
ADG1201/ADG1202
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1 VDD
2 GND
3 VSS
4S
5D
6 IN
VDD 1
6 IN
ADG1201/
GND 2 ADG1202 5 D
VSS
3
TOP VIEW
(Not to Scale)
4
S
Figure 2. SOT-23 Pin Configuration
Description
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Most Negative Power Supply Potential.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
Table 5. ADG1201/ADG1202 Truth Table
ADG1201 IN
ADG1202 IN
10
01
Switch Condition
On
Off
Rev. 0 | Page 6 of 16

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ADG1202 pdf, datenblatt
ADG1201/ADG1202
TERMINOLOGY
IDD
The positive supply current.
ISS
The negative supply current.
VD (VS)
The analog voltage on Terminal D and Terminal S.
RON
The ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
IS (Off)
The source leakage current with the switch off.
ID (Off)
The drain leakage current with the switch off.
ID, IS (On)
The channel leakage current with the switch on.
VINL
The maximum input voltage for Logic 0.
VINH
The minimum input voltage for Logic 1.
IINL (IINH)
The input current of the digital input.
CS (Off)
The off switch source capacitance, measured with reference
to ground.
CD (Off)
The off switch drain capacitance, measured with reference
to ground.
CD, CS (On)
The on switch capacitance, measured with reference to ground.
CIN
The digital input capacitance.
tON
The delay between applying the digital control input and the
output switching on. See Figure 26.
tOFF
The delay between applying the digital control input and the
output switching off. See Figure 26.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
ACPSRR (AC Power Supply Rejection Ratio)
Measures the ability of a part to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of
signal on the output to the amplitude of the modulation is
the ACPSRR.
Rev. 0 | Page 12 of 16

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