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8V43FS92432 Schematic ( PDF Datasheet ) - IDT

Teilenummer 8V43FS92432
Beschreibung 1360MHz Dual Output LVPECL Clock Synthesizer
Hersteller IDT
Logo IDT Logo 




Gesamt 27 Seiten
8V43FS92432 Datasheet, Funktion
1360MHz Dual Output LVPECL
Clock Synthesizer
8V43FS92432
DATA SHEET
General Description
The 8V43FS92432 is a 3.3V-compatible, PLL based clock
synthesizer targeted for high performance clock generation in
mid-range to high-performance telecom, networking, and computing
applications. With output frequencies from 21.25MHz to 1360MHz
and the support of two differential PECL output signals, the device
meets the needs of the most demanding clock applications.
The 8V43FS92432 is a programmable high-frequency clock source
(clock synthesizer). The internal PLL generates a high-frequency
output signal based on a low-frequency reference signal. The
frequency of the output signal is programmable and can be changed
on the fly for frequency margining purpose.
The internal crystal oscillator uses the external quartz crystal as the
basis of its frequency reference. Alternatively, a LVCMOS compatible
clock signal can be used as a PLL reference signal. The frequency of
the internal crystal oscillator is divided by a selectable divider and
then multiplied by the PLL. Its output is scaled by a divider that is
configured by either the I2C or parallel interfaces. The crystal
oscillator frequency fXTAL, the PLL pre-divider P, the feedback-divider
M, and the PLL post-divider N determine the output frequency. The
feedback path of the PLL is internal.
The PLL post-divider N is configured through either the I2C or the
parallel interfaces, and can provide one of six division ratios (2, 4, 8,
16, 32, 64). This divider extends the performance of the part while
providing a 50% duty cycle. The high-frequency outputs, QA and QB,
are differential and are capable of driving a pair of transmission lines
terminated 50to VCC – 2.0 V. The second high-frequency output,
QB, can be configured to run at either 1x or 1/2x of the clock
frequency or the first output (QA). The positive supply voltage for the
internal PLL is separated from the power supply for the core logic
and output drivers to minimize noise induced jitter.
The configuration logic has two sections: I2C and parallel. The
parallel interface uses the values at the M[9:0], NA[2:0], NB, and P
parallel inputs to configure the internal PLL dividers. The parallel
programming interface has priority over the serial I2C interface. The
serial interface is I2C compatible and provides read and write access
to the internal PLL configuration registers. The lock state of the PLL
is indicated by the LVCMOS-compatible LOCK output.
Features
21.25MHz to 1360MHz synthesized clock output signal
Two differential, LVPECL-compatible high-frequency outputs
Output frequency programmable through 2-wire I2C bus or
parallel interface
On-chip crystal oscillator for reference frequency generation
Alternative LVCMOS compatible reference clock input
Synchronous clock stop functionality for both outputs
LOCK indicator output (LVCMOS)
LVCMOS compatible control inputs
Fully integrated PLL
3.3-V power supply
48-lead LQFP
48-lead Pb-free package available
SiGe Technology
Ambient temperature range: –40°C to +85°C
Applications
Programmable clock source for server, computing, and
telecommunication systems
Frequency margining
Oscillator replacement
8V43FS92432 REVISION 1 10/28/15
1 ©2015 INTEGRATED DEVICE TECHNOLOGY, INC.






8V43FS92432 Datasheet, Funktion
8V43FS92432 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Table 4. Absolute Maximum Ratings
Symbol Characteristics
VCC
VIN
VI
VOUT
IIN
IOUT
TS
TFUNC
TJ
HBM
CDM
Supply Voltage
DC Input Voltage
Crystal Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
Functional Temperature Range
Operating Junction Temperature
ESD Human Body Model1
ESD Charged Device Model1
NOTE 1. According to JEDEC/JS-001-2012/JESD22-C101E.
Condition
Min
-0.3
-0.3
0
-0.3
-65
TA = -40
Max
3.6
VCC + 0.3
2
VCC + 0.3
±20
±50
125
TA = +85
125
2000
500
Unit
V
V
V
V
mA
mA
°C
°C
°C
V
V
1360MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER
6
REVISION 1 10/28/15

6 Page









8V43FS92432 pdf, datenblatt
8V43FS92432 DATA SHEET
LOAD and GET are inverse command to each other. LOAD updates
the PLL dividers and GET updates the configuration registers. A fast
and convenient way to change the PLL frequency is to use the INC
(increment M) and DEC (decrement M) commands of the
synthesizer. INC (DEC) directly increments (decrements) the
PLL-feedback divider M and immediately changes the PLL
frequency by the smallest step G (see Table 8 for the frequency
granularity G). The INC and DEC commands are designed for
multiple and rapid PLL frequency changes as required in frequency
margining applications. INC and DEC do not require the user to
update the PLL dividers by the LOAD command, INC and DEC do
not update the PLL_L and PLL_H registers either (use LOAD for an
initial PLL divider setting and, if desired, use GET to read the PLL
configuration). Note that the synthesizer does not check any
boundary conditions such as the VCO frequency range. Applying
the INC and DEC commands could result in invalid VCO frequencies
(VCO frequency beyond lock range).
Register Maps
Table 14. Configuration Registers
Address Name
Content
Access
0x00 PLL_L
Least significant 8 bits of M
R/W
0x01
0xF0
PLL_H
CMD
Most significant 2 bits of M, P, NA,
NB, and lock state
Command register (write only)
R/W
W only
Register 0x00 (PLL_L) contains the least significant bits of the PLL
feedback divider M.
Table 15. PLL_L (0x00, R/W) Register
Bit 7 6 5 4 3 2 1 0
Name M7 M6 M5 M4 M3 M2 M1 M0
Register content:
M[7:0]
PLL feedback-divider M, bits [7–0]
Register 0x01 (PLL_H) contains the two most significant bits of the
PLL feedback divider M, four bits to control the PLL post-dividers N
and the PLL pre-divider P. The bit 0 in PLL_H register indicates the
lock condition of the PLL and is set by the synthesizer automatically.
The LOCK state is a copy of the PLL lock signal output (LOCK). A
write-access to LOCK has no effect.
Table 16. PLL_H (0x01, R/W) Register
Bit 7 6 5 4 3 2 1 0
Name M9 M8 NA2 NA1 NA0 NB P LOCK
Register content:
M[9:8] PLL feedback-divider M, bits 9–8
NA[2:0]
NB
P
PLL post-divider NA, see Table 10
PLL post-divider NB, see Table 11
PLL pre-divider P, see Table 9
LOCK Copy of LOCK output signal (read-only)
Note that the LOAD command is required to update the PLL dividers
by the content of both PLL_L and PLL_H registers.
Register 0xF0 (CMD) is a write-only command register.
The purpose of CMD is to provide a fast way to increase or decrease
the PLL frequency and to update the registers. The register accepts
four commands, INC (increment M), DEC (decrement M), LOAD and
GET (update registers). It is recommended to write the INC, DEC
commands only after a valid PLL configuration is achieved. INC and
DEC only affect the M-divider of the PLL (PLL feedback). Applying
INC and DEC commands can result in a PLL configuration beyond
the specified lock range and the PLL may loose lock. The
8V43FS92432 does not verify the validity of any commands such as
LOAD, INC, and DEC. The INC and DEC commands change the
PLL feedback divider without updating PLL_L and PLL_H.
Table 17. CMD (0xF0): PLL Command (Write-Only)
Command Op-Code
Description
INC xxxx0001b Increase internal PLL frequency
(0x01)
M= M+1
DEC
xxxx0010b
(0x02)
Decrease internal PLL frequency
M= M-1
LOAD
xxxx0100b
Update the PLL divider config.
(0x04) PLL divider M, N, P= PLL_L, PLL_H
GET
xxxx1000b Update the configuration registers
(0x08) PLL_L, PLL_H= PLL divider M, N, P
I2C — Register Access in Parallel Mode
The 8V43FS92432 supports the configuration of the synthesizer
through the parallel interlace (nPLOAD = 0) and serial interface
(nPLOAD = 1). Register contents and the divider configurations are
not changed when the user switches from parallel mode to serial
mode. However, when switching from serial mode to parallel mode,
the PLL dividers immediately reflect the logical state of the hardware
pins M[9:0], NA[2:0], NB, and P.
Applications using the parallel interface to obtain a PLL configuration
can use the serial interface to verify the divider settings. In parallel
mode (nPLOAD = 0), the 8V43FS92432 allows read-access to
PLL_L and PLL_H through I2C (if nPLOAD = 0, the current PLL
configuration is stored in PLL_L, PLL_H. The GET command is not
necessary and also not supported in parallel mode). After changing
from parallel to serial mode (nPLOAD = 1), the last PLL
configuration is still stored in PLL_L, PLL_H. The user now has full
write and read access to both configuration registers through the I2C
bus and can change the configuration at any time.
Table 18. PLL Configuration in Parallel and Serial Modes
PLL
Configuration
M[9:0]
NA[2:0]
NB
P
LOCK status
Parallel
Set pins M9–M0
Set pins NA2...NA0
Set pin NB
Set pin P
LOCK pin 26
Serial (Registers
PLL_L, PLL_H)
M[9:0] (R/W)
NA[2:0] (R/W)
NB (R/W)
P (R/W)
LOCK (Read only)
1360MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER
12
REVISION 1 10/28/15

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