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PDF PEX8532 Data sheet ( Hoja de datos )
| Número de pieza | PEX8532 | |
| Descripción | Flexible & Versatile PCI Express Switches | |
| Fabricantes | PLX | |
| Logotipo |  |
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. Version 1.1 2004
Features
PEX 8532 & PEX 8516§ PEX 8532 General Features
o 32-lane PCI Express switch
o Integrated SerDes
o Eight configurable ports
(x1, x2, x4, x8, x16)
o 35mm x35mm, 680 pin enhanced
Flexible & Versatile PCI Express™ Switches
PBGA package, 6.5 Watts
§ PEX 8516 General Features
Multi-purpose and Feature Rich PCI Express Switch Family
o 16-lane PCI Express switch
o Integrated SerDes
o Four configurable ports
The 32-lane PEX 8532 and 16-lane PEX 8516 products offer PCI Express
switching capability conforming to the latest revision of the PCI Express Base
(x1, x2, x4, x8)
specification. These products enable users to add scalable high bandwidth, non-
o 27mm x 27mm, 312 pin enhanced
PBGA package, 3.5 Watts
§ PEX 8532 & PEX 8516 Common
blocking interconnection to a wide variety of applications including servers, storage
systems, communications platforms , blade servers, and embedded-control products.
The PEX 8532/16 products can be used as fanout, aggregation, or peer-to-peer
Features
o Standards Compliant
- PCI Express Base Specification, r1.0a
switches, and are equally we ll-suited to fabric backplane and intelligent I/O
module applications.
- PCI Standard SHPC Specification, r1.1
o High Performance
- Non-blocking Switch Fabric
Highly Flexible Port Configurations
The PEX 8532/16 offer highly configurable ports. There are a maximum of 8 ports
- Full Line rate
(4 for PEX 8516) that can be configured to any legal width from x1 to x16 (x8 max
o Configurable Non-transparent port for
Multi-Host or Intelligent I/O Support
o Flexible Configuration
- Eight (four for PEX8516) highly flexible
and configurable ports
- Flexible lane width/port x2(x1), x4, x8,
for PEX 8516), in any combination to support your specific bandwidth needs. The
ports can be symmetric (each port having the same lane width) or asymmetric
(ports having different lane widths). If you can think of a port/lane combination, you
can configure it! Any of the ports can be designated as the upstream port, and you
can even dynamically change the upstream port.
(x16 for PEX 8532 only)
- Configurable with strapping pins,
End-to-end Packet Integrity
EEPROM, or Host software
The PEX family provides end-to-end CRC protection (ECRC) and Poison bit
- Lane and polarity reversal
o PCI Express Power Management
- Link power management states: L0, L0s,
L1, L2/L3 Ready, and L3
support to enable designs that require guaranteed error -free packets. These
features are optional in the PCI Express specification, but PLX provides them across
its entire PEX product line.
- Device states: D0 and D3hot
o Quality of Service (QoS)
- Two Virtual Channels/port
- Eight Traffic Classes/port
Non-Transparent “Bridging” in a PCI Express Switch
The PEX 8532/16 product family supports full non-transparent bridging functionality
to allow implementation of multi-host systems and intelligent I/O modules in
- Fixed and WRR Virtual Channel
applications such as communications, storage, and blade servers. To ensure quick
arbitration
- Round robin port arbitration
o Reliability, Availability, Serviceability
(RAS)
product migration, the non-transparency features are implemented in the same
fashion as in standard PCI applications.
Non-transparent bridges allow systems to isolate memory domains by presenting the
- Standard Hot-Plug Controller
- Upstream port as hot -plug client
- Transaction Layer end-to-end CRC
- Poison bit
- Error reporting in addition to advanced
processor subsystem as an endpoint, rather than another memory system. Base
address registers are used to translate addresses; doorbell registers are used to send
interrupts between the address domains; and scratchpad registers are accessible from
both address domains to allow inter-processor communication.
error reporting support of PCI Express
- Per port performance monitoring
• Average packet size, number of
packets, CRC errors
Two Virtual Channels
The PEX 8532/16 products support 2 full-featured Virtual Channels (VCs) and a full
8 Traffic Classes (TCs). The mapping of Traffic Classes to port-specific Virtual
- JTAG boundary scan
Channels allows for different mappings for different ports. In addition, the devices
offer user-selectable Virtual Channel arbitration algorithms to enable users to fine
tune the Quality of Service (QoS) required for a specific application.
Low Power with Granular SerDes Control
The PEX 8532/16 provide low power capability that is fully compliant with the PCI
Express power management specification. In addition, the SerDes physical links can
be turned off when unused for even lower power.
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| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet PEX8532.PDF ] | |
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