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GAL20V8Z Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer GAL20V8Z
Beschreibung Zero Power E2CMOS PLD
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 20 Seiten
GAL20V8Z Datasheet, Funktion
Features
• ZERO POWER E2CMOS TECHNOLOGY
— 100µA Standby Current
— Input Transition Detection on GAL20V8Z
— Dedicated Power-down Pin on GAL20V8ZD
— Input and Output Latching During Power Down
• HIGH PERFORMANCE E2CMOS TECHNOLOGY
— 12 ns Maximum Propagation Delay
— Fmax = 83.3 MHz
— 8 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Output Drive
— UltraMOS® Advanced CMOS Technology
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Similar to Standard GAL20V8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Battery Powered Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
GAL20V8Z
GAL20V8ZD
Zero Power E2CMOS PLD
Functional Block Diagram
I/CLK
I
I
I/DPP
IMUX
CLK
8 OLMC
8 OLMC
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
I 8 OLMC
OE
I
IMUX
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/OE
Description
The GAL20V8Z and GAL20V8ZD, at 100 µA standby current and
12ns propagation delay provides the highest speed and lowest
power combination PLD available in the market. The
GAL20V8Z/ZD is manufactured using Lattice Semiconductor's ad-
vanced zero power E2CMOS process, which combines CMOS with
Electrically Erasable (E2) floating gate technology.
The GAL20V8Z uses Input Transition Detection (ITD) to put the
device in standby mode and is capable of emulating the full func-
tionality of the standard GAL20V8. The GAL20V8ZD utilizes a
dedicated power-down pin (DPP) to put the device in standby mode.
It has 19 inputs available to the AND array.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
DIP
PLCC
I/CLK
I
I
4 2 28 26
I/DPP 5
2 5 I/O/Q I/D P P
I
I7
NC
I9
GAL20V8Z
GAL20V8ZD
Top View
I/O/Q
2 3 I/O/Q
NC
2 1 I/O/Q
I
I
I
I
I
I/O/Q
I
I 1 1 1 2 1 4 1 6 1 8 1 9 I/O/Q
I
I
GND
1 24 Vcc
2 23 I
3 GAL 22
4 20V8Z 21
5 20V8ZD 20
6 19
I/O/Q
I/O/Q
I/O/Q
I/O/Q
7 18 I/O/Q
8 17 I/O/Q
9 16 I/O/Q
10 15 I/O/Q
11 14 I
12 13 I/OE
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
December 1997
20v8zzd_03
1






GAL20V8Z Datasheet, Funktion
Specifications GAL20V8Z
GAL20V8ZD
Complex Mode
In the Complex mode, macrocells are configured as output only or
I/O functions.
Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1(2) and
13(16) are always available as data inputs into the AND array.
Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It
cannot be used as functional input.
Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 15(18) & 22(26)) do not have input capability.
Designs requiring eight I/Os can be implemented in the Registered
mode.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
XOR
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 16(19) through Pin 21(25) are configured to this
function.
XOR
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 15(18) and Pin 22(26) are configured to this
function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
6

6 Page









GAL20V8Z pdf, datenblatt
Specifications GAL20V8Z
Specifications GGAALL2200VV88ZZDD
AC Switching Characteristics
Over Recommended Operating Conditions
TEST
PARAMETER COND1.
DESCRIPTION
tpd A Input or I/O to Combinational Output
tco A Clock to Output Delay
tcf2 Clock to Feedback Delay
tsu Setup Time, Input or Feedback before Clock
th Hold Time, Input or Feedback after Clock
A Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
COM
-12
MIN. MAX.
3 12
COM
-15
UNITS
MIN. MAX.
3 15 ns
2 8 2 10 ns
67
ns
10 15
ns
0 0 ns
55 40 MHz
fmax3
twh
twl
ten
tdis
A Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with
No Feedback
Clock Pulse Duration, High
Clock Pulse Duration, Low
B Input or I/O to Output Enabled
B OE to Output Enabled
C Input or I/O to Output Disabled
C OE to Output Disabled
62.5 45.5 MHz
83.3 62.5 MHz
68
68
12 15
12 15
15 15
12 15
ns
ns
ns
ns
ns
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.
12

12 Page





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