PDF 8T39S11A Data sheet ( Hoja de datos )

Número de pieza	8T39S11A
Descripción	Crystal or Differential to Differential Clock Fanout Buffer
Fabricantes	IDT
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No Preview Available ! Crystal or Differential-to-Differential Clock Fanout Buffer 8T39S11A Datasheet General Description The 8T39S11A is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by a single-ended clock.The selected signal is distributed to ten differential outputs which can be configured as LVPECL, LVDS or HSCL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for a signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply. Features • Two differential reference clock input pairs • Differential input pairs can accept the following differential input levels: LVPECL, LVDS, HCSL, HSTL or Single Ended • Crystal Input accepts 10MHz to 40MHz Crystal or Single Ended Clock • Maximum Output Frequency LVPECL - 2GHz LVDS - 2GHz HCSL - 250MHz LVCMOS - 250MHz • Two banks, each has five differential output pairs that can be configured as LVPECL or LVDS or HCSL • One single-ended reference output with synchronous enable to avoid clock glitch • Output skew: 80ps (maximum) (Bank A and Bank B at the same output level) • Part-to-part skew: 200ps (typical) • Additive RMS phase jitter @ 156.25MHz: 5.6fs RMS (10kHz - 1 MHz), typical @ 3.3V/ 3.3V 34.7fs RMS (12kHz - 20MHz), typical @ 3.3V/ 3.3V • Supply voltage modes: VDD/VDDO 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V • -40°C to 85°C ambient operating temperature • Lead-free (RoHS 6) packaging ©2015 Integrated Device Technology, Inc. 1 December 17, 2015 1 page Function Tables Table 3: REF_SELx Function Table Control Input REF_SEL[1:0] Selected Input Reference Clock 00 (default) CLK0, nCLK0 01 CLK1, nCLK1 10 XTAL 11 XTAL 8T39S11A Datasheet Table 4: OE_SE Function Table1 OE_SE REFOUT 0 (default) High-Impedance 1 Enabled NOTE 1. Synchronous output enable to avoid clock glitch. Table 5: Input/Output Operation Table, OE_SE Input Status OE_SE REF_SEL [1:0] CLKx and nCLKx 0 (default) Don’t care Don’t Care 1 10 or 11 Don’t Care CLK0 and nCLK0 are both open circuit CLK0 and nCLK0 are tied to ground 1 00 (default) CLK0 is high, nCLK0 is low CLK0 is low, nCLK0 is high CLK1 and nCLK1 are both open circuit CLK1 and nCLK1 are tied to ground 1 01 CLK1 is high, nCLK1 is low CLK1 is low, nCLK1 is high Table 6: Input/Output Operation Table, SMODEA Input Status SMODEA[1:0] REF_SEL[1:0] CLKx and nCLKx 11 Don’t care Don’t Care 00, 01 or 10 10 or 11 Don’t Care CLK0 and nCLK0 are both open circuit 00, 01 or 10 00 (default) CLK0 and nCLK0 are tied to ground CLK0 is high, nCLK0 is low CLK0 is low, nCLK0 is high CLK1 and nCLK1 are both open circuit 00, 01 or 10 01 CLK1 and nCLK1 are tied to ground CLK1 is high, nCLK1 is low CLK1 is low, nCLK1 is high ©2015 Integrated Device Technology, Inc. 5 Output State REFOUT High Impedance Fanout crystal oscillator Logic Low Logic Low Logic High Logic Low Logic Low Logic Low Logic High Logic Low Output State QA[4:0], nQA[4:0] High Impedance Fanout crystal oscillator QA[4:0] = Low nQA[4:0] = High QA[4:0] = Low nQA[4:0] = High QA[4:0] = High nQA[4:0] = Low QA[4:0] = Low nQA[4:0] = High QA[4:0] = Low nQA[4:0] = High QA[4:0] = Low nQA[4:0] = High QA[4:0] = High nQA[4:0] = Low QA[4:0] = Low nQA[4:0] = High December 17, 2015 5 Page 8T39S11A Datasheet AC Electrical Characteristics Table 20: AC Characteristics, VDD = VDDOA = VDDOB = VDDOREF = 3.3V±5%, GND = 0V, TA = -40°C to 85°C 1 2 Symbol Parameter Test Conditions Minimum Typical Maximum Units LVDS, LVPECL Outputs 2000 MHz fOUT Output Frequency HCSL Outputs LVCMOS Outputs 250 MHz 250 MHz Buffer Additive Phase Jitter, RMS: Integration Range 12kHz - 20MHz REF_SEL[1:0] = 00 or 01 Clock Frequency = 156.25MHz; Input Clock from 8T49NS010A, Input Clock Jitter = 86.6fs; SMODEA/B[1:0] = 00 tjit Buffer Additive Phase Jitter, RMS: Integration Range 10kHz - 1MHz REF_SEL[1:0] = 00 or 01 Clock Frequency = 156.25MHz; Input Clock from 8T49NS010A, Input Clock Jitter = 60.8fs; SMODEA/B[1:0] = 00 34.7 5.6 fs fs LVPECL Outputs NF Noise Floor LVDS Outputs Offset Freq. >10MHz; 156.25MHz Clock Freq. HCSL Outputs -159.1 -157.0 -156.0 dBc/Hz dBc/Hz dBc/Hz tjit(Ø) RMS Phase Jitter; 25MHz Integration Range: 100Hz - 1MHz REF_SEL[1:0] = 10 or 113 0.176 ps tPD tsk(o) tsk(pp) VOH VOL VCROSS VCROSS Propagation Delay4 CLK0, nCLK0 or CLK1, nCLK1 to any Qx, nQx Outputs Output Skew5 6 Part-to-Part Skew6 7 Voltage High8 9 HCSL Outputs Voltage Low8 10 HCSL Outputs Absolute Crossing Voltage8 11 12 HCSL Outputs Total Variation of VCROSS over all Edges8 11 13 HCSL Outputs SMODEA/B[1:0] = 00 SMODEA/B[1:0] = 01 SMODEA/B[1:0] = 10 TA = 25°C DC Measurement, RT = 50 to GND CL 5pF RT = 50 to GND CL 5pF 0.28 0.28 0.90 520 -150 160 200 0.75 ns 0.75 ns 2.65 ns 80 ps ps 920 mV 150 mV 460 mV 140 mV Rise/Fall Edge Rate3 14 15 HCSL Outputs 0.6 4.0 V/ns LVPECL Outputs 20% to 80% 150 300 ps tR / tF Output Rise/Fall Time LVDS Outputs HCSL Outputs 20% to 80% 20% to 80% 150 300 ps 400 650 ps REFOUT 20% to 80% 450 750 ps odc Output Duty Cycle16 with Crystal Input with External 50%/ 50% Duty Cycle Clock Input 45 45 55 % 55 % MUX_ISOLATION MUX Isolation 156.25MHz 75 dB NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the de- vice is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 2. All LVDS and LVPECL parameters characterized up to 1.5GHz. HCSL parameters characterized up to 250MHz. ©2015 Integrated Device Technology, Inc. 11 December 17, 2015 11 Page

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