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8L30210 Schematic ( Datenblatt PDF ) - IDT

Teilenummer 8L30210
Beschreibung Crystal or Differential to LVCMOS/LVTTL Clock Buffer
Hersteller IDT
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Gesamt 20 Seiten
		
8L30210 Datasheet, Funktion
Crystal or Differential to LVCMOS/
LVTTL Clock Buffer
8L30210
DATA SHEET
General Description
The 8L30210 is a low skew, 1-to-10 LVCMOS / LVTTL Fanout Buffer.
The low impedance LVCMOS/LVTTL outputs are designed to drive
50series or parallel terminated transmission lines.
The 8L30210 is characterized at full 3.3V and 2.5V, mixed 3.3V/2.5V,
3.3V/1.8V, 3.3V/1.5V, 2.5V/1.8V and 2.5V/1.5V output operating
supply modes. The input clock is selected from two differential clock
inputs or a crystal input. The differential input can be wired to accept
a single-ended input. The internal oscillator circuit is automatically
disabled if the crystal input is not selected.
Features
Ten LVCMOS / LVTTL outputs up to 200MHz
Differential input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
Crystal Oscillator Interface
Crystal input frequency range: 10MHz to 40MHz
Additive RMS phase jitter: 30fs (typical)
Synchronous output enable to avoid clock glitch
Power supply modes:
Core / Output
3.3V / 3.3V
2.5V / 2.5V
3.3V / 2.5V
3.3V / 1.8V
3.3V / 1.5V
2.5V / 1.8V
2.5V / 1.5V
Supports case temperature up to 105°C
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
Pin Assignment
32 31 30 29 28 27 26 25
Q0 1
24 Q9
VDDO 2
23 VDDO
00
Q1 3
22 Q8
GNDO 4
21 GNDO
01 8L30210
Q2 5
20 Q7
VDDO 6
19 VDDO
1x
Q3 7
18 Q6
Q4 8
17 Q5
9 10 11 12 13 14 15 16
8L30210 REVISION 2 11/24/15
32-pin, 5mm x 5mm VFQFN Package
1 ©2015 Integrated Device Technology, Inc.






8L30210 Datasheet, Funktion
8L30210 DATA SHEET
Table 4B. Power Supply DC Characteristics, VDD = 2.5V±5%, VDDO = 2.5V±5% or 1.8V±0.15V or 1.5V±0.1V,
TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
VDD Power Supply Voltage
2.375 2.5 2.625
2.375 2.5 2.625
VDDO
Output Supply Current
1.65 1.8 1.95
1.4 1.5 1.6
IDD
IDDO
Power Supply Current
Output Supply Current
No Clock Input, Outputs Unloaded
OE = 1, VDDO = 2.5V±5%, Outputs Unloaded
OE = 1, VDDO = 1.8V±0.15V, Outputs Unloaded
OE = 1, VDDO = 1.5V±0.1V, Outputs Unloaded
19
2
2
2
Units
V
V
V
V
mA
mA
mA
mA
Table 4C. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
VIH Input High Voltage
VIL Input Low Voltage
IIH Input High Current OE, SEL[1:0]
IIL Input Low Current OE, SEL[1:0]
VOH Output High Voltage
VOL Output Low Voltage
VDD = 3.3V±5%
VDD = 2.5V±5%
VDD = 3.3V±5%
VDD = 2.5V±5%
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
IOH = -100µA
IOL = 100µA
Minimum
2.2
1.7
-0.3
-0.3
Typical
-5
VDDO – 0.1
Maximum
0.8
0.7
150
0.1
Units
V
V
V
V
µA
µA
V
V
CRYSTAL OR DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK BUFFER
6
REVISION 2 11/24/15

6 Page







8L30210 pdf, datenblatt
8L30210 DATA SHEET
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential
signals. Both signals must meet the VPP and VCMR input
requirements. Figures 5A to 5D show interface examples for the CLK
/nCLK input with built-in 50terminations driven by the most
common driver types. The input interfaces suggested here are
examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
Figure 5A. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
*R3
HCSL
*R4
3.3V
CLK
nCLK
Differential
Input
Figure 5B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 5C. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 5D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
CRYSTAL OR DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK BUFFER
12
REVISION 2 11/24/15

12 Page


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