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83905 Schematic ( PDF Datasheet ) - IDT

Teilenummer 83905
Beschreibung 1:6 Crystal-to-LVCMOS/LVTTL Fanout Buffer
Hersteller IDT
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Gesamt 21 Seiten
83905 Datasheet, Funktion
Low Skew, 1:6 Crystal-to-LVCMOS/
LVTTL Fanout Buffer
83905
Datasheet
General Description
The 83905 is a low skew, 1-to-6 LVCMOS / LVTTL Fanout Buffer.
The low impedance LVCMOS/LVTTL outputs are designed to
drive 50series or parallel terminated transmission lines. The
effective fanout can be increased from 6 to 12 by utilizing the
ability of the outputs to drive two series terminated lines.
The 83905 is characterized at full 3.3V, 2.5V, and 1.8V, mixed
3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply
mode. Guaranteed output and part-to-part skew characteristics
along with the 1.8V output capabilities makes the 83905 ideal for
high performance, single ended applications that also require a
limited output voltage.
Pin Assignments
Features
Six LVCMOS / LVTTL outputs
Outputs able to drive 12 series terminated lines
Crystal Oscillator Interface
Crystal input frequency range: 10MHz to 40MHz
Output skew: 80ps (maximum)
RMS phase jitter @ 25MHz, (100Hz – 1MHz): 0.26ps (typical),
VDD = VDDO = 2.5V
Offset
Noise Power
100Hz.................-129.7 dBc/Hz
1kHz ...................-144.4 dBc/Hz
10kHz .................-147.3 dBc/Hz
100kHz ...............-157.3 dBc/Hz
5V tolerant enable inputs
Synchronous output enables
Operating power supply modes:
Full 3.3V, 2.5V, 1.8V
Mixed 3.3V core/2.5V output operating supply
Mixed 3.3V core/1.8V output operating supply
Mixed 2.5V core/1.8V output operating supply
0°C to 70°C ambient operating temperature
Lead-free (RoHS 6) packaging
83905
20-Lead VFQFN
4mm x 4mm x 0.925mm
package body
K Package
Top View
20 19 18 17 16
GND 1
15 BCLK5
GND 2
14 VDDO
BCLK0 3
VDDO 4
13 BCLK4
12 GND
BCLK1 5
11 GND
6 7 8 9 10
Block Diagram
83905
16-Lead SOIC, 150 Mil
3.9mm x 9.9mm x 1.38mm
package body
M Package
Top View
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
G Package
Top View
XTAL_OUT
ENABLE2
GND
BCLK0
VDDO
BCLK1
GND
BCLK2
1
2
3
4
5
6
7
8
16 XTAL_IN
15 ENABLE1
14 BCLK5
13 VDDO
12 BCLK4
11 GND
10 BCLK3
9 VDD
XTAL_IN
XTAL_OUT
ENABLE 1
ENABLE 2
SYNCHRONIZE
SYNCHRONIZE
BCLK0
BCLK1
BCLK2
BCLK3
BCLK4
BCLK5
©2016 Integrated Device Technology, Inc.
1
Revision D September 27, 2016






83905 Datasheet, Funktion
83905 Datasheet
AC Electrical Characteristics
Table 6A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
fMAX
Using External Crystal
Output Frequency Using External Clock
Source NOTE 1
tsk(o) Output Skew; NOTE 2, 3
tjit(Ø) RMS Phase Jitter (Random); NOTE 4
25MHz, Integration Range:
100Hz – 1MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
tEN
Output Enable
Time; NOTE 5
ENABLE1
ENABLE2
tDIS
Output Disable
Time; NOTE 5
ENABLE1
ENABLE2
Minimum
10
DC
200
48
Typical
0.13
Maximum Units
40 MHz
100 MHz
80 ps
ps
800 ps
52 %
4 cycles
4 cycles
4 cycles
4 cycles
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at ƒ fMAX using a crystal input unless noted otherwise.
Terminated at 50to VDDO/2.
NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: See phase noise plot.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
Table 6B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
fMAX
Using External Crystal
Output Frequency Using External Clock
Source NOTE 1
tsk(o) Output Skew; NOTE 2, 3
tjit
RMS Phase Jitter (Random); NOTE 4
25MHz, Integration Range:
100Hz – 1MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
tEN
Output Enable
Time; NOTE 5
ENABLE1
ENABLE2
tDIS
Output Disable
Time; NOTE 5
ENABLE1
ENABLE2
Minimum
10
DC
200
47
Typical
0.26
Maximum Units
40 MHz
100 MHz
80 ps
ps
800 ps
53 %
4 cycles
4 cycles
4 cycles
4 cycles
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at ƒ fMAX using a crystal input unless noted otherwise.
Terminated at 50to VDDO/2.
NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: See phase noise plot.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc.
6
Revision D September 27, 2016

6 Page









83905 pdf, datenblatt
83905 Datasheet
Application Information
Crystal Input Interface
Figure 2 shows an example of 83905 crystal interface with a
parallel resonant crystal. The frequency accuracy can be fine
tuned by adjusting the C1 and C2 values. For a parallel crystal with
loading capacitance CL = 18pF, to start with, we suggest C1 =
15pF and C2 = 15pF. These values may be slightly fine tuned
further to optimize the frequency accuracy for different board
layouts. Slightly increasing the C1 and C2 values will slightly
reduce the frequency. Slightly decreasing the C1 and C2 values
will slightly increase the frequency. For the oscillator circuit below,
R1 can be used, but is not required. For new designs, it is
recommended that R1 not be used.
X1
18pF Parallel Crystal
XTAL_IN
C1
15p
0
XTAL_OUT
C2 R1 (optional)
15p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50applications, R1
and R2 can be 100. This can also be accomplished by removing
R1 and making R2 50. By overdriving the crystal oscillator, the
device will be functional, but note, the device performance is
guaranteed by using a quartz crystal.
VDD
VDD
R1
Ro Rs 50Ω
0.1µf
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
©2016 Integrated Device Technology, Inc.
12
Revision D September 27, 2016

12 Page





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