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831724 Schematic ( PDF Datasheet ) - IDT

Teilenummer 831724
Beschreibung Differential Clock/Data Multiplexer
Hersteller IDT
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Gesamt 22 Seiten
831724 Datasheet, Funktion
Differential Clock/Data Multiplexer
831724
Datasheet
General Description
The 831724 is a high-performance, differential HCSL clock/data
multiplexer and fanout buffer. The device is designed for the
multiplexing and fanout of high-frequency clock and data signals.
The device has two differential, selectable clock/data inputs. The
selected input signal is distributed to four low-skew differential HCSL
outputs. Each input pair accepts HCSL, LVDS and LVPECL levels.
The 831724 is characterized to operate from a 3.3V power supply.
Guaranteed input, output-to-output and part-to-part skew
characteristics make the 831724 ideal for those clock and data
distribution applications demanding well-defined performance and
repeatability. The 831724 supports the clock multiplexing and
distribution of PCI Express Generation 1, 2, and 3 clock signals.
Features
2:1 differential clock/data multiplexer with fanout
Two selectable, differential inputs
Each differential input pair can accept the following levels: HCSL,
LVDS, LVPECL.
Four differential HCSL outputs
Maximum input/output clock frequency: 350MHz
Maximum input/output data rate: 700Mb/s (NRZ)
LVCMOS interface levels for all control inputs
PCI Express Gen 1,2,3 jitter compliant
Input skew: 165ps (maximum)
Output skew: 175ps (maximum)
Part-to-part skew: 450ps (maximum)
Full 3.3V supply voltage
Available in lead-free (RoHS 6) package
-40°C to 85°C ambient operating temperature
Block Diagram
IREF
Pulldown
CLK0 Pullup/down
nCLK0 Pulldown
Pullup/down
CLK1
nCLK1 Pulldown
Pullup
Pullup
Pullup
Pullup
SEL
0
1
QA
nQA
QB
nQB
QC
nQC
QD
nQD
Pin Assignment
32 31 30 29 28 27 26 25
VDD 1
24 nc
nOED 2
23 nOEC
CLK0 3
22 nc
nCLK0 4
21 nc
CLK1 5
20 nc
nCLK1 6
19 nc
nOEA 7
18 SEL
VDD 8
17 nc
9 10 11 12 13 14 15 16
831724I
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision B November 16, 2016






831724 Datasheet, Funktion
831724 Datasheet
Table 5B. HCSL AC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
fOUT
tjit
Output Frequency
Buffer Additive Phase
Jitter, RMS
100MHz, Integration Range:
12kHz – 20MHz
tPD
Propagation Delay;
NOTE 1, 3
Any CLK, nCLK to any Q, nQ
tsk(o)
Output Skew; NOTE 3,15
Across all outputs
tsk(i)
Input Skew; NOTE 2, 3
tsk(pp)
Part-to-Part Skew;
NOTE 3, 4
MUXISOL
Rising
Edge Rate
Falling
Edge Rate
TSTABLE
Mux Isolation
Rising Edge Rate;
NOTE 5, 6
Falling Edge Rate;
NOTE 5, 6
Time before VRB is
allowed; NOTE 5, 7
ƒ = 100MHz
fOUT 125MHz
fOUT 125MHz
fOUT 125MHz
fOUT 125MHz
VRB
Ringback Voltage;
NOTE 5, 7
VMAX
Absolute Maximum Output
Voltage; NOTE 8, 9
VMIN
Absolute Minimum Output
Voltage; NOTE 8, 10
VCROSS
Absolute Crossing Voltage;
NOTE 8, 11, 12
VCROSS
Total Variation of VCROSS
over all edges;
NOTE 8, 11, 13
odc
Output Duty Cycle;
NOTE 14
fOUT 125MHz
fOUT 125MHz
Minimum Typical Maximum Units
350 MHz
0.357
0.480
ps
2.7 3.9 ns
175 ps
165 ps
450 ps
94 dB
0.6 4.2 V/ns
0.6 6.8 V/ns
0.6 4.5 V/ns
0.6 6.7 V/ns
500 ps
-100
100 mV
1150
mV
-300
mV
200 550 mV
140 mV
46 54 %
40 60 %
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between input paths on the same device, using the same input signal levels, measured at one specific output at the
differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: Measurement taken from differential waveform.
NOTE 6: Measurement from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 7: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100 differential range. See Parameter Measurement Information Section.
NOTE 8: Measurement taken from single-ended waveform.
NOTE 9: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 10: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
Notes continued on next page.
NOTE 11: Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ.
See Parameter Measurement Information Section
©2016 Integrated Device Technology, Inc
6
Revision B November 16, 2016

6 Page









831724 pdf, datenblatt
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The block diagram below shows
the most frequently used Common Clock Architecture in which a
copy of the reference clock is provided to both ends of the PCI
Express Link.
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs
are modeled as well as the phase interpolator in the receiver. These
transfer functions are called H1, H2, and H3 respectively. The
overall system transfer function at the receiver is:
Hts= H3s  H1s– H2s
The jitter spectrum seen by the receiver is the result of applying this
system transfer function to the clock spectrum X(s) and is:
Ys= Xs  H3s  H1s– H2s
In order to generate time domain jitter numbers, an inverse Fourier
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
831724 Datasheet
individual transfer functions as well as the overall transfer function
Ht.
PCIe Gen 2A Magnitude of Transfer Function
PCI Express Common Clock Architecture
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist (e.g
for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is
reported in peak-peak.
PCIe Gen 2B Magnitude of Transfer Function
For PCI Express Gen 3, one transfer function is defined and the
evaluation is performed over the entire spectrum. The transfer
function parameters are different from Gen 1 and the jitter result is
reported in RMS.
PCIe Gen 1 Magnitude of Transfer Function
For PCI Express Gen 2, two transfer functions are defined with 2
evaluation ranges and the final jitter number is reported in rms. The
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz
(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the
PCIe Gen 3 Magnitude of Transfer Function
For a more thorough overview of PCI Express jitter analysis
methodology, please refer to IDT Application Note: PCI Express
Reference Clock Requirements.
©2016 Integrated Device Technology, Inc
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Revision B November 16, 2016

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