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EPF10K30 Schematic ( PDF Datasheet ) - Altera Corporation

Teilenummer EPF10K30
Beschreibung Embedded Programmable Logic Device Family
Hersteller Altera Corporation
Logo Altera Corporation Logo 




Gesamt 30 Seiten
EPF10K30 Datasheet, Funktion
January 2003, ver. 4.2
Includes
FLEX 10KA
FLEX 10K
® Embedded Programmable
Logic Device Family
Data Sheet
Features...
The industry’s first embedded programmable logic device (PLD)
family, providing System-on-a-Programmable-Chip (SOPC)
integration
– Embedded array for implementing megafunctions, such as
efficient memory and specialized logic functions
– Logic array for general logic functions
High density
– 10,000 to 250,000 typical gates (see Tables 1 and 2)
– Up to 40,960 RAM bits; 2,048 bits per embedded array block
(EAB), all of which can be used without reducing logic capacity
System-level features
– MultiVoltTM I/O interface support
– 5.0-V tolerant input pins in FLEX® 10KA devices
– Low power consumption (typical specification less than 0.5 mA
in standby mode for most devices)
– FLEX 10K and FLEX 10KA devices support peripheral
component interconnect Special Interest Group (PCI SIG) PCI
Local Bus Specification, Revision 2.2
– FLEX 10KA devices include pull-up clamping diode, selectable
on a pin-by-pin basis for 3.3-V PCI compliance
– Select FLEX 10KA devices support 5.0-V PCI buses with eight or
fewer loads
– Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming any device logic
Table 1. FLEX 10K Device Features
Feature
Typical gates (logic and RAM) (1)
Maximum system gates
Logic elements (LEs)
Logic array blocks (LABs)
Embedded array blocks (EABs)
Total RAM bits
Maximum user I/O pins
EPF10K10
EPF10K10A
10,000
31,000
576
72
3
6,144
150
EPF10K20
20,000
63,000
1,152
144
6
12,288
189
EPF10K30
EPF10K30A
30,000
69,000
1,728
216
6
12,288
246
EPF10K40
40,000
93,000
2,304
288
8
16,384
189
EPF10K50
EPF10K50V
50,000
116,000
2,880
360
10
20,480
310
Altera Corporation
DS-F10K-4.2
1






EPF10K30 Datasheet, Funktion
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
The FLEX 10K architecture is similar to that of embedded gate arrays, the
fastest-growing segment of the gate array market. As with standard gate
arrays, embedded gate arrays implement general logic in a conventional
“sea-of-gates” architecture. In addition, embedded gate arrays have
dedicated die areas for implementing large, specialized functions. By
embedding functions in silicon, embedded gate arrays provide reduced
die area and increased speed compared to standard gate arrays. However,
embedded megafunctions typically cannot be customized, limiting the
designer’s options. In contrast, FLEX 10K devices are programmable,
providing the designer with full control over embedded megafunctions
and general logic while facilitating iterative design changes during
debugging.
Each FLEX 10K device contains an embedded array and a logic array. The
embedded array is used to implement a variety of memory functions or
complex logic functions, such as digital signal processing (DSP),
microcontroller, wide-data-path manipulation, and data-transformation
functions. The logic array performs the same function as the sea-of-gates
in the gate array: it is used to implement general logic, such as counters,
adders, state machines, and multiplexers. The combination of embedded
and logic arrays provides the high performance and high density of
embedded gate arrays, enabling designers to implement an entire system
on a single device.
FLEX 10K devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers the EPC1, EPC2, EPC16, and EPC1441 configuration devices,
which configure FLEX 10K devices via a serial data stream. Configuration
data can also be downloaded from system RAM or from Altera’s
BitBlasterTM serial download cable or ByteBlasterMVTM parallel port
download cable. After a FLEX 10K device has been configured, it can be
reconfigured in-circuit by resetting the device and loading new data.
Because reconfiguration requires less than 320 ms, real-time changes can
be made during system operation.
FLEX 10K devices contain an optimized interface that permits
microprocessors to configure FLEX 10K devices serially or in parallel, and
synchronously or asynchronously. The interface also enables
microprocessors to treat a FLEX 10K device as memory and configure the
device by writing to a virtual memory location, making it very easy for the
designer to reconfigure the device.
6 Altera Corporation

6 Page









EPF10K30 pdf, datenblatt
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 4. FLEX 10K Embedded Array Block
Dedicated Inputs & Chip-Wide
Global Signals
Reset
Row Interconnect
(1)
6
8, 4, 2, 1
DQ
8, 9, 10, 11
DQ
DQ
2, 4, 8, 16
Data
In
Data
Out
DQ
24
Address
RAM/ROM
256 × 8
512 × 4
1,024 × 2
2,048 × 1
WE
2, 4, 8, 16
Column
Interconnect
EAB Local Interconnect (1)
Note:
(1) EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, and EPF10K50V devices have
22 EAB local interconnect channels; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, and EPF10K250A devices
have 26.
12 Altera Corporation

12 Page





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