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PDF EM6GC16EWKE Data sheet ( Hoja de datos )
| Número de pieza | EM6GC16EWKE | |
| Descripción | 64M x 16 bit DDR3 Synchronous DRAM | |
| Fabricantes | Etron Technology | |
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EtronTech
EM6GC16EWKE
64M x 16 bit DDR3 Synchronous DRAM (SDRAM)
Advance (Rev. 1.0, Jul. /2015)
Features
• JEDEC Standard Compliant
• Power supplies: VDD & VDDQ = +1.5V ± 0.075V
• Operating temperature: 0~95°C (TC)
• Supports JEDEC clock jitter specification
• Fully synchronous operation
• Fast clock rate: 667/800/933MHz
• Differential Clock, CK & CK#
• Bidirectional differential data strobe
- DQS & DQS#
• 8 internal banks for concurrent operation
• 8n-bit prefetch architecture
• Pipelined internal architecture
• Precharge & active power down
• Programmable Mode & Extended Mode registers
• Additive Latency (AL): 0, CL-1, CL-2
• Programmable Burst lengths: 4, 8
• Burst type: Sequential / Interleave
• Output Driver Impedance Control
• 8192 refresh cycles / 64ms
- Average refresh period
7.8µs @ 0°C TC +85°C
3.9µs @ +85°C TC +95°C
• Write Leveling
• ZQ Calibration
• Dynamic ODT (Rtt_Nom & Rtt_WR)
• RoHS compliant
• Auto Refresh and Self Refresh
• 96-ball 8 x 13 x 1.0mm FBGA package
- Pb and Halogen Free
Overview
The 1Gb Double-Data-Rate-3 DRAMs is double data
rate architecture to achieve high-speed operation. It is
internally configured as an eight bank DRAM.
The 1Gb chip is organized as 8Mbit x 16 I/Os x 8
bank devices. These synchronous devices achieve
high speed double-data-rate transfer rates of up to
1866 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3
DRAM key features and all of the control and address
inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the
cross point of differential clocks (CK rising and CK#
falling). All I/Os are synchronized with differential DQS
pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.075V
power supply and are available in BGA packages.
Table 1. Ordering Information
Part Number
Clock Frequency
EM6GC16EWKE-15H
667MHz
EM6GC16EWKE-12H
800MHz
EM6GC16EWKE-10H
933MHz
WK: indicates 8 x 13 x 1.0mm FBGA package
E: indicates Generation Code
H: indicates Pb and Halogen Free
Data Rate
1333Mbps/pin
1600Mbps/pin
1866Mbps/pin
Power Supply
VDD 1.5V, VDDQ 1.5V
VDD 1.5V, VDDQ 1.5V
VDD 1.5V, VDDQ 1.5V
Package
FBGA
FBGA
FBGA
Table 2. Speed Grade Information
Speed Grade
Clock Frequency
DDR3-1333
DDR3-1600
DDR3-1866
667MHz
800MHz
933MHz
CAS Latency
9
11
13
tRCD (ns)
13.5
13.75
13.91
tRP (ns)
13.5
13.75
13.91
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.
1 page  
EtronTech
EM6GC16EWKE
Ball Descriptions
Table 3. Ball Descriptions
Symbol Type
Description
CK, CK#
Input
Differential Clock: CK and CK# are driven by the system clock. All SDRAM input signals
are sampled on the crossing of positive edge of CK and negative edge of CK#. Output
(Read) data is referenced to the crossings of CK and CK# (both directions of crossing).
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes
LOW synchronously with clock, the internal clock is suspended from the next clock cycle
and the state of output and burst address is frozen as long as the CKE remains LOW.
When all banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes.
BA0-BA2
Input Bank Address: BA0-BA2 define to which bank the BankActivate, Read, Write, or Bank
Precharge command is being applied.
A0-A12
Input
Address Inputs: A0-A12 are sampled during the BankActivate command (row address
A0-A12) and Read/Write command (column address A0-A9 with A10 defining Auto
Precharge).
A10/AP
Input
Auto-Precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation.
(HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH).
A12/BC#
Input Burst Chop: A12/BC# is sampled during Read and Write commands to determine if burst
chop (on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped).
CS#
Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. It is considered part of
the command code.
RAS#
Input
Row Address Strobe: The RAS# signal defines the operation commands in conjunction
with the CAS# and WE# signals and is latched at the crossing of positive edges of CK
and negative edge of CK#. When RAS# and CS# are asserted "LOW" and CAS# is
asserted "HIGH," either the BankActivate command or the Precharge command is
selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate
command is selected and the bank designated by BA is turned on to the active state.
When the WE# is asserted "LOW," the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
CAS#
Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the crossing of positive
edges of CK and negative edge of CK#. When RAS# is held "HIGH" and CS# is asserted
"LOW," the column access is started by asserting CAS# "LOW." Then, the Read or Write
command is selected by asserting WE# “HIGH " or “LOW".
WE#
Input
Write Enable: The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the crossing of positive edges of CK and
negative edge of CK#. The WE# input is used to select the BankActivate or Precharge
command and Read or Write command.
LDQS,
LDQS#
UDQS
UDQS#
Input /
Output
Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe
is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM.
LDQS is for DQ0~7, UDQS is for DQ8~15. The data strobes LDOS and UDQS are paired
with LDQS# and UDQS# to provide differential pair signaling to the system during both
reads and writes.
LDM,
UDM
Input Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle.
LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
Rev. 1.0
5
Jul. /2015
5 Page 
EtronTech
EM6GC16EWKE
Register Definition
Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode Registers,
provided by the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register Set
(MRS) command. As the default values of the Mode Registers are not defined, contents of Mode Registers must be
fully initialized and/or re-initialized, i.e., written, after power up and/or reset for proper operation. Also the contents of
the Mode Registers can be altered by re-executing the MRS command during normal operation. When
programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address
fields within the accessed mode register must be redefined when the MRS command is issued. MRS command and
DLL Reset do not affect array contents, which mean these commands can be executed any time after power-up
without affecting the array contents.
The mode register set command cycle time, tMRD is required to complete the write operation to the mode
register and is the minimum time required between two MRS commands shown in Figure of tMRD timing.
Figure 6. tMRD timing
T0
CK#
CK
COMMAND VALID
ADDRESS
VALID
CKE
T1
VALID
VALID
T2
VALID
VALID
Ta0 Ta1 Tb0 Tb1 Tb2 Tc0
Tc1
MRS
VALID
NOP/DES
NOP/DES
VALID
VALID
MRS
VALID
NOP/DES
NOP/DES
VALID
VALID
VALID
VALID
Tc2
VALID
VALID
Settings
Old Settings
ODT
ODT
RTT_Nom ENABLED prior and/or after MRS command
VALID
VALID
ODTLoff + 1
RTT_Nom DISABLED prior and after MRS command
VALID
VALID
VALID
VALID
tMRD
Updating Settings
tMOD
VALID
VALID
VALID
VALID
VALID
New Settings
VALID
VALID
VALID
TIME BREAK
Don't Care
Rev. 1.0
11
Jul. /2015
11 Page | ||
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