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EM6AA160 Schematic ( PDF Datasheet ) - Etron Technology

Teilenummer EM6AA160
Beschreibung 16M x 16 bit DDR Synchronous DRAM
Hersteller Etron Technology
Logo Etron Technology Logo 




Gesamt 30 Seiten
EM6AA160 Datasheet, Funktion
EtronTech
EM6AA160
Etron Confidential
16M x 16 bit DDR Synchronous DRAM (SDRAM)
Preliminary (Rev. 1.3, Mar. /2014)
Features
Fast clock rate: 250/200MHz
Differential Clock CK & CK
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
Internal pipeline architecture
Four internal banks, 4M x 16-bit for each bank
Programmable Mode and Extended Mode registers
- CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
Individual byte write mask control
DM Write Latency = 0
Auto Refresh and Self Refresh
8192 refresh cycles / 64ms
Precharge & active power down
Power supplies: VDD & VDDQ = 2.5V ± 0.2V
Interface: SSTL_2 I/O Interface
Package: 66 Pin TSOP II, 0.65mm pin pitch
- Pb free and Halogen free
Package: 60-Ball, 8x13x1.2 mm (max) TFBGA
- Pb free and Halogen Free
Overview
The EM6AA160 SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 256
Mbits. It is internally configured as a quad 4M x 16
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CK). Data outputs occur at both rising edges of CK
and CK . Read and write accesses to the SDRAM
are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses
begin with the registration of a BankActivate
command which is then followed by a Read or Write
command. The EM6AA160 provides programmable
Read or Write burst lengths of 2, 4, or 8. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst sequence. The refresh functions, either Auto or
Self Refresh are easy to use. In addition, EM6AA160
features programmable DLL option. By having a
programmable mode register and extended mode
register, the system can choose the most suitable
modes to maximize its performance. These devices
are well suited for applications requiring high
memory bandwidth, result in a device particularly
well suited to high performance main memory and
graphics applications.
Table 1. Ordering Information
Part Number
Clock Frequency Data Rate
EM6AA160TSC-4G
250MHz
500Mbps/pin
EM6AA160TSC-5G
200MHz
400Mbps/pin
EM6AA160BKC-4H
250MHz
500Mbps/pin
EM6AA160BKC-5H
200MHz
400Mbps/pin
TS: indicates TSOP II Package
BK: indicates TFBGA Package
C: indicates Generation Code
G: indicates Pb free and Halogen Free for TSOPII Package
H: indicates Pb free and Halogen Free for TFBGA Package
Package
TSOPII
TSOPII
TFBGA
TFBGA
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.






EM6AA160 Datasheet, Funktion
EtronTech
EM6AA160
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 3
shows the truth table for the operation commands.
Table 3. Truth Table (Note (1), (2))
Command
State CKEn-1 CKEn DM BA0,1 A10 A0-9, 11-12 CS RAS CAS
BankActivate
Idle(3) H X X V Row address L L H
BankPrecharge
Any H X X V L X
L LH
PrechargeAll
Any H X X X H X
L LH
Write
Write and AutoPrecharge
Active(3)
Active(3)
H
H
X X V L Column L H L
X
X
V
H
address
(A0 ~ A8)
L
H
L
Read
Read and Autoprecharge
Active(3)
Active(3)
H
H
X X V L Column L H L
X
X
V
H
address
(A0 ~ A8)
L
H
L
Mode Register Set
Idle H X X
OP code
LLL
Extended MRS
Idle H X X
OP code
LLL
No-Operation
Any H X X X X X
L HH
Burst Stop
Active(4) H
XX XX
X
L HH
Device Deselect
Any H X X X X X
HXX
AutoRefresh
Idle H H X X X X
LLL
SelfRefresh Entry
Idle H L X X X X
LLL
SelfRefresh Exit
Idle L H X X X X
HXX
(SelfRefresh)
L HH
Precharge Power Down
Mode Entry
Idle H L X X X X
HXX
L HH
Precharge Power Down
Mode Exit
Any
(PowerDown)
L
HX XX
X
HXX
L HH
Active Power Down Mode Active H L X X X
Entry
X
HXX
LVV
Active Power Down Mode Any
Exit
(PowerDown)
L
HX XX
X
HXX
L HH
Data Input Mask Disable Active H X L X X
X
XXX
Data Input Mask Enable(5) Active H X H X X
X
X
Note: 1. V=Valid data, X=Don't Care, L=Low level, H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA signal.
4. Device state is 2, 4, and 8 burst operation.
5. LDM and UDM can be enabled respectively.
X
X
WE
H
L
L
L
L
H
H
L
L
H
L
X
H
H
X
H
X
H
X
H
X
V
X
H
X
X
Etron Confidential
6
Rev. 1.3
Mar. /2014

6 Page









EM6AA160 pdf, datenblatt
EtronTech
EM6AA160
Table 15. D.C. Characteristics (VDD = 2.5V ± 0.2V, TA = 0~70 °C)
Parameter & Test Condition
Symbol
OPERATING CURRENT: One bank; Active-Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs
changing once per clock cycle; Address and control inputs
IDD0
changing once every two clock cycles.
OPERATING CURRENT : One bank; Active-Read-
Precharge; BL=4; tRC=tRC(min); tCK=tCK(min); lout=0mA;
IDD1
Address and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All
banks idle; power-down mode; tCK=tCK(min); CKE=LOW
IDD2P
PRECHARGE FLOATING STANDBY CURRENT: CKE =
HIGH; CS =HIGH(DESELECT); All banks idle; tCK=tCK(min); IDD2F
Address and control inputs changing once per clock cycle;
VIN=VREF for DQ, DQS and DM
PRECHARGE QUIET STANDBY CURRENT: CKE = HIGH;
CS =HIGH(DESELECT); All banks idle; tCK=tCK(min);
Address and other control input stadle at HIGH or LOW;
IDD2Q
VIN=VREF for DQ, DQS and DM
ACTIVE POWER-DOWN STANDBY CURRENT : one bank
active; power-down mode; CKE=LOW; tCK=tCK(min)
IDD3P
ACTIVE STANDBY CURRENT : CS =HIGH;CKE=HIGH; one
bank active ; tRC=tRC(max);tCK=tCK(min);Address and control IDD3N
inputs changing once per clock cycle; DQ,DQS,and DM
inputs changing twice per clock cycle
OPERATING CURRENT BURST READ : BL=2; READS;
Continuous burst; one bank active; Address and control
inputs changing once per clock cycle; tCK=tCK(min);
IDD4R
lout=0mA;50% of data changing on every transfer
OPERATING CURRENT BURST Write : BL=2; WRITES;
Continuous Burst ;one bank active; address and control
inputs changing once per clock cycle; tCK=tCK(min);
IDD4W
DQ,DQS,and DM changing twice per clock cycle; 50% of
data changing on every transfer
AUTO REFRESH CURRENT : tRC=tRFC(min); tCK=tCK(min) IDD5
SELF REFRESH CURRENT: Sell Refresh Mode ; CKE
0.2V;tCK=tCK(min)
BURST OPERATING CURRENT 4 bank operation:
Four bank interleaving READs; BL=4;with Auto Precharge;
tRC=tRC(min); tCK=tCK(min); Address and control inputs
change only during Active, READ , or WRITE command
IDD6
IDD7
-4 -5
Max.
70 65
80 70
55
30 30
25 20
20 20
60 55
120 100
120 100
100 100
22
160 140
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA 1
mA
Etron Confidential
12
Rev. 1.3
Mar. /2014

12 Page





SeitenGesamt 30 Seiten
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