PDF EM6A9320BIB Data sheet ( Hoja de datos )

Número de pieza	EM6A9320BIB
Descripción	4M x 32 bit DDR Synchronous DRAM
Fabricantes	Etron Technology
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No Preview Available ! EtronTech EM6A9320BIB Etron Confidential 4M x 32 bit DDR Synchronous DRAM (SDRAM) Advanced (Rev. 1.2, Aug. /2013) Features • Fast clock rate: 200/250 MHz • Differential Clock CK & CK input • 4 Bi-directional DQS. Data transactions on both edges of DQS (1DQS / Byte) • DLL aligns DQ and DQS transitions • Edge aligned data & DQS output • Center aligned data & DQS input • 4 internal banks, 1M x 32-bit for each bank • Programmable mode and extended mode registers - CAS Latency: 2, 2.5, 3 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleave • All inputs except DQ’s & DM are at the positive edge of the system clock • 4 individual DM control for write masking only • Auto Refresh and Self Refresh • 4096 refresh cycles / 64ms • Power supplies: VDD & VDDQ = 2.5V ± 0.2V • Interface: SSTL_2 I/O compatible • 144-ball 12 x 12 x 1.4mm LFBGA package -Pb and Halogen Free Overview The EM6A9320 DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 128 Mbits. It is internally configured as a quad 1M x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK . Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command, which is then followed by a Read or Write command. The EM6A9320 provides programmable Read or Write burst lengths of 2, 4, 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.The refresh functions, either Auto or Self Refresh are easy to use. In addition, EM6A9320 features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth, result in a device particularly well suited to high performance main memory and graphics applications. Table1. Ordering Information Part Number Clock Frequency Data Rate EM6A9320BIB-4H 250MHz 500Mbps/pin EM6A9320BIB-5H 200MHz 400Mbps/pin BI: indicates LFBGA package B: indicates generation code H: indicates Pb and Halogen Free for LFBGA Package Power Supply VDD 2.5V, VDDQ 2.5V VDD 2.5V, VDDQ 2.5V Package LFBGA LFBGA Etron Technology, Inc. No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc. reserves the right to change products or specification without notice. 1 page EtronTech EM6A9320BIB VDDQ VSSQ VREF NC Supply Supply Supply - DQ Power: Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Reference Voltage for Inputs: +0.5 x VDDQ No Connect: No internal connection, these pins suggest to be left unconnected. Etron Confidential 5 Rev. 1.2 Aug. /2013 5 Page EtronTech EM6A9320BIB Table 17. D.C. Characteristics (VDD=2.5V ± 0.2V, TA =0~70°C) Parameter & Test Condition Symbol OPERATING CURRENT: One bank; Active-Precharge; tRC=tRC (min); tCK=tCK (min); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles. OPERATING CURRENT : One bank; Active-Read-Precharge; BL=4; tRC=tRC(min); tCK=tCK(min); lout=0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; power-down mode; tCK=tCK(min); CKE=LOW IDD0 IDD1 IDD2P IDLE STANDBY CURRENT : CKE = HIGH; CS =HIGH(DESELECT); All banks idle; tCK=tCK(min); Address and control inputs changing once per clock cycle; VIN=VREF for DQ, DQS and DM ACTIVE POWER-DOWN STANDBY CURRENT : one bank active; power- down mode; CKE=LOW; tCK=tCK(min) IDD2N IDD3P ACTIVE STANDBY CURRENT : CS =HIGH;CKE=HIGH; one bank active ; tRC=tRC(max);tCK=tCK(min);Address and control inputs changing once per IDD3N clock cycle; DQ,DQS,and DM inputs changing twice per clock cycle OPERATING CURRENT BURST READ : BL=2; READs; Continuous burst; one bank active; Address and control inputs changing once per clock IDD4R cycle; tCK=tCK(min); lout=0mA;50% of data changing on every transfer OPERATING CURRENT BURST Write : BL=2; WRITES; Continuous Burst ;one bank active; address and control inputs changing once per clock cycle; tCK=tCK(min); DQ,DQS,and DM changing twice per clock cycle; 50% IDD4W of data changing on every transfer AUTO REFRESH CURRENT : tRC=tRFC(min); tCK=tCK(min) SELF REFRESH CURRENT: Self Refresh Mode ; CKE 0.2V;tCK=tCK(min) IDD5 IDD6 BURST OPERATING CURRENT 4 bank operation: Four bank interleaving READs; BL=4;with Auto Precharge; tRC=tRC(min); tCK=tCK(min); Address and control inputs change only during Active, READ , or WRITE command IDD7 -4 -5 Max. 220 210 260 240 75 75 100 100 75 75 230 220 440 420 440 420 330 300 66 600 570 Note: 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. 2. All voltages are referenced to VSS. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 4. Power-up sequence is described in later page. Unit mA mA mA mA mA mA mA mA mA mA mA Etron Confidential 11 Rev. 1.2 Aug. /2013 11 Page

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