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ADF4356 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF4356
Beschreibung 6.8 GHz Wideband Synthesizer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADF4356 Datasheet, Funktion
Data Sheet
6.8 GHz Wideband Synthesizer
with Integrated VCO
ADF4356
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 53.125 MHz to 6800 MHz
Integer channel: −227 dBc/Hz
Fractional channel: −225 dBc/Hz
Integrated RMS jitter (1 kHz to 20 MHz): 97 fs for 6 GHz output
Fractional-N synthesizer and integer-N synthesizer
Pin compatible to the ADF4355
High resolution, 52-bit modulus
Phase frequency detector (PFD) operation to 125 MHz
Reference input frequency operation to 600 MHz
Maintains frequency lock over −40°C to +85°C
Low phase noise, voltage controlled oscillator (VCO)
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
Analog and digital power supplies: 3.3 V
Charge pump and VCO power supplies: 5.0 V typical
Logic compatibility: 1.8 V
Programmable output power level
RF output mute function
Supported in the ADIsimPLL design tool
The ADF4356 allows implementation of fractional-N or integer-N
phase-locked loop (PLL) frequency synthesizers when used with
an external loop filter and an external reference frequency. A series
of frequency dividers at another frequency output permits
operation from 53.125 MHz to 6800 MHz.
The ADF4356 has an integrated VCO with a fundamental
output frequency ranging from 3400 MHz to 6800 MHz. In
addition, the VCO frequency is connected to divide by 1, 2, 4, 8,
16, 32, or 64 circuits that allow the user to generate RF output
frequencies as low as 53.125 MHz. For applications that require
isolation, the RF output stage can be muted. The mute function
is both pin- and software-controllable.
Control of all on-chip registers is through a simple 3-wire interface.
The ADF4356 operates with analog and digital power supplies
ranging from 3.15 V to 3.45 V, with charge pump and VCO
supplies from 4.75 V to 5.25 V. The ADF4356 also contains
hardware and software power-down modes.
APPLICATIONS
Wireless infrastructure (LTE, W-CDMA, TD-SCDMA,
WiMAX, GSM, PCS, DCS)
Point to point/point to multipoint microwave links
Satellites/VSATs
Test equipment/instrumentation
Clock generation
FUNCTIONAL BLOCK DIAGRAM
CE
DVDD
AVDD
DVDD
VP
VVCO VRF
REFINA
REFINB
CLK
DATA
LE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
INTEGER FRACTION MODULUS
VALUE
VALUE
VALUE
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
LOCK
DETECT
MULTIPLEXER
CHARGE
PUMP
PHASE
COMPARATOR
VCO
CORE
÷1/2/4/8/16/
32/64
MUXOUT
CREG1
CREG2
CPOUT
OUTPUT
STAGE
OUTPUT
STAGE
VTUNE
VREF
VBIAS
VREGVCO
RFOUTA+
RFOUTA–
PDBRF
RFOUTB+
RFOUTB–
MULTIPLEXER
ADF4356
AGND
SDGND
CPGND
Figure 1.
AGNDRF AGNDVCO
Rev. 0
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Technical Support
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ADF4356 Datasheet, Funktion
ADF4356
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VRF, DVDD, AVDD to GND1
AVDD to DVDD
VP, VVCO to GND1
CPOUT to GND1
Digital Input/Output Voltage to GND1
Analog Input/Output Voltage to GND1
REFINA, REFINB to GND1
REFINA to REFINB
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Electrostatic Discharge (ESD)
Charged Device Model
Human Body Model
Rating
−0.3 V to +3.6 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to VP + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
±2.1 V
−40°C to +85°C
−65°C to +125°C
150°C
260°C
40 sec
1000 V
2000 V
1 GND = AGND = SDGND = AGNDRF = AGNDVCO = CPGND = 0 V.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Data Sheet
The ADF4356 is a high performance RF integrated circuit with
an ESD rating of 2 kV and is ESD sensitive. Take proper
precautions for handling and assembly.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 4. Thermal Resistance
Package Type
CP-32-121
θJA
27.3
Unit
°C/W
1 Test Condition 1: thermal impedance simulated values are based on use of a
PCB with the thermal impedance paddle soldered to GND1.
TRANSISTOR COUNT
The transistor count for the ADF4356 is 134,486 (CMOS) and
3874 (bipolar).
ESD CAUTION
Rev. 0 | Page 6 of 35

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ADF4356 pdf, datenblatt
ADF4356
Data Sheet
THEORY OF OPERATION
REFERENCE INPUT SECTION
INT, FRACx, MODx, and R Counter Relationship
Figure 20 shows the reference input stage. The reference input
can accept both single-ended and differential signals. Use the
reference mode bit (Register 4, Bit DB9) to select the signal. To
use a differential signal on the reference input, program this bit
high. In this case, SW1 and SW2 are open, SW3 and SW4 are
closed, and the current source that drives the differential pair of
transistors switches on. The differential signal buffers and provides
an emitter-coupled logic (ECL) to the CMOS converter. When a
single-ended signal is used as the reference, program Bit DB9
in Register 4 to 0. Connect the single-ended reference signal to
REFINA. In this case, SW1 and SW2 are closed, SW3 and SW4
are open, and the current source that drives the differential pair
of transistors switches off.
REFERENCE
INPUT MODE
The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in
conjunction with the R counter, make it possible to generate
output frequencies spaced by fractions of the PFD frequency
(fPFD). For more information, see the RF Synthesizer—A Worked
Example section.
Calculate the RF VCO frequency (VCOOUT) by
VCOOUT = fPFD × N
(1)
where:
VCOOUT is the output frequency of the VCO (without using the
output divider).
fPFD is the frequency of the phase frequency detector.
N is the desired value of the feedback counter, N.
Calculate fPFD by
fPFD = REFIN × ((1 + D)/(R × (1 + T)))
(2)
REFINA
SW1
85k
SW2
BUFFER
SW3
TO
R COUNTER
MULTIPLEXER
AVDD
ECL TO CMOS
BUFFER
REFINB
2.5k
2.5k
BIAS
SW4
GENERATOR
Figure 20. Reference Input Stage, Differential Mode
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. Determine the division ratio by the INT, FRAC1, FRAC2,
and MOD2 values that this divider comprises.
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
RF N COUNTER
N = INT +
N COUNTER
FRAC1 +
FRAC2
MOD2
MOD1
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
TO PFD
INT
REG
FRAC1
REG
FRAC2
VALUE
MOD2
VALUE
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
T is the REFIN divide by 2 bit (0 or 1).
N comprises
FRAC1FRAC2
N INT
MOD2
MOD1
(3)
where:
INT is the 16-bit integer value (23 to 32,767 for the 4/5
prescaler, and 75 to 65,535 for the 8/9 prescaler).
FRAC1 is the numerator of the primary modulus (0 to 16,777,215).
FRAC2 is the numerator of the 28-bit auxiliary modulus
(0 to 268,435,455).
MOD2 is the programmable, 28-bit auxiliary fractional
modulus (2 to 268,435,455).
MOD1 is a 24-bit primary modulus with a fixed value of 224 =
16,777,216.
Equation 3 results in a very fine frequency resolution with no
residual frequency error. To apply this formula, take the
following steps:
1. Calculate N by dividing VCOOUT/fPFD.
2. The integer value of this number forms INT.
3. Subtract the INT value from the full N value.
4. Multiply the remainder by 224.
5. The integer value of this number forms FRAC1.
6. Calculate MOD2 based on the channel spacing (fCHSP) by
MOD2 = fPFD/GCD(fPFD, fCHSP)
(4)
Figure 21. RF N Divider
where:
GCD(fPFD, fCHSP) is the greatest common divider of the PFD
frequency and the channel spacing frequency.
fCHSP is the desired channel spacing frequency.
7. Calculate FRAC2 by the following equation:
FRAC2 = ((N INT) × 224 FRAC1)) × MOD2
(5)
Rev. 0 | Page 12 of 35

12 Page





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