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DS2432 Schematic ( PDF Datasheet ) - Maxim Integrated

Teilenummer DS2432
Beschreibung 1Kb Protected 1-Wire EEPROM
Hersteller Maxim Integrated
Logo Maxim Integrated Logo 




Gesamt 17 Seiten
DS2432 Datasheet, Funktion
ABRIDGED DATA SHEET
DS2432
1Kb Protected 1-Wire EEPROM
with SHA-1 Engine
FEATURES
1128 Bits of 5V EEPROM Memory
Partitioned Into Four Pages of 256 Bits, a
64-Bit Write-Only Secret, and Up to Five
General-Purpose Read/Write Registers
On-Chip 512-Bit ISO/IEC 10118-3 SHA-1
Engine to Compute 160-Bit Message
Authentication Codes (MACs) and to
Generate Secrets
Write Access Requires Knowledge of the
Secret and the Capability of Computing and
Transmitting a 160-Bit MAC as
Authorization
Secret and Data Memory Can Be Write
Protected (All or Page 0 Only) or Put in
EPROM-Emulation Mode (“Write to 0”,
Page 1)
Unique, Factory-Lasered and Tested 64-Bit
Registration Number Assures Absolute
Traceability Because No Two Parts Are Alike
Built-In Multidrop Controller Ensures
Compatibility with Other 1-Wire® Net
Products
Reduces Control, Address, Data, and Power
to a Single Data Pin
Directly Connects to a Single Port Pin of a
Microprocessor and Communicates at Up to
15.3kbps
Overdrive Mode Boosts Communication
Speed to 90.9kbps
Low-Cost 6-Lead TSOC Surface-Mount
Package or Solder-Bumped UCSP™ Package
Reads and Writes Over a Wide Voltage
Range of 2.8V to 5.25V from -40°C to +85°C
PIN CONFIGURATIONS
TOP VIEW
GND 1
1-Wire 2
NC 3
TSOC
(150 mils)
6 NC
5 NC
4 NC
A1 MARK
UCSP
(TOP VIEW WITH LASER
A DS2432
MARK, CONTACTS NOT
VISIBLE)
B
yywwrr
A2 = 1-WIRE
C ###xx
A3 = GND
ALL OTHER BUMPS: NC
1234
yywwrr = DATE/REVISION
###xx = LOT NUMBER
REFER TO THE PACKAGE RELIABILITY REPORT FOR
IMPORTANT GUIDELINES ON QUALIFIED USAGE CONDITIONS.
ORDERING INFORMATION
PART
TEMP
RANGE
PIN-
PACKAGE
DS2432P+
-40°C to +85°C 6 TSOC
DS2432P+T&R -40°C to +85°C 6 TSOC
DS2432X-S+
-40°C to +85°C
8 UCSP (2.5k
pcs, T&R)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
Request Full Data Sheet at:
www.maximintegrated.com/DS2432
1-Wire is a registered trademark and UCSP is a trademark of Maxim Integrated Products, Inc.
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219-0003; Rev 9/12






DS2432 Datasheet, Funktion
ABRIDGED DATA SHEET
DS2432
WRITING WITH VERIFICATION
To write data to the DS2432, the scratchpad has to be used as intermediate storage. First the master issues
the Write Scratchpad command to specify the desired target address, followed by the data to be written to
the scratchpad. Note that writes to data memory must be performed on 8-byte boundaries with the 3 LSBs
of the target address (T2..T0) equal to 000b. If T2..T0 are sent with non-zero values, the device will set
these bits to zero and will write to the modified address upon completion of the command sequence. In
addition, the entire 8-byte scratchpad will be copied to memory when commanded, therefore eight bytes
of data should be written into the scratchpad to ensure that the data to be copied is known. Under certain
conditions (see the Write Scratchpad command) the master will receive an inverted CRC-16 of the
command, address (actual address sent) and data at the end of the write scratchpad command sequence.
Note that the CRC is calculated based on the actual target address sent and not the modified address in the
case of a non-zero T2..T0. Knowing this CRC value, the master can compare it to the value it has
calculated itself to decide if the communication was successful and proceed to the Copy Scratchpad
command. If the master could not receive the CRC-16, it should send the Read Scratchpad command to
verify data integrity. As preamble to the scratchpad data, the DS2432 repeats the target address TA1 and
TA2 and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the
scratchpad or there was a loss of power since data was last written to the scratchpad. The master does not
need to continue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag
together with a cleared PF flag indicates that the device did not recognize the Write command. If
everything went correctly, both flags are cleared. Now the master can continue reading and verifying
every data byte. After the master has verified the data, it can send the Copy Scratchpad command, for
example. This command must be followed exactly by the data of the three address registers TA1, TA2
and E/S. The master should obtain the contents of these registers by reading the scratchpad.
MEMORY AND SHA-1 FUNCTION COMMANDS
This section describes the commands and flow charts to use the memory and SHA-1 engine of the device.
It includes Tables 1 to 4 and Figure 7. Please refer to the full version of the data sheet.
SHA-1 COMPUTATION ALGORITHM
The SHA-1 computation is adapted from the Secure Hash Standard SHA-1 document as it can be
downloaded from the NIST website (http://www.itl.nist.gov/fipspubs/fip180-1.htm). Further details are
found in the full version of the data sheet.
1-Wire BUS SYSTEM
The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the
DS2432 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system
is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling
(signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state during
specific time slots that are initiated on the falling edge of sync pulses from the bus master.
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DS2432 pdf, datenblatt
ABRIDGED DATA SHEET
DS2432
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10
MASTER TX “RESET PULSE” MASTER RX “PRESENCE PULSE”
VPULLUP
VPULLUP MIN
VIH MIN
VIL MAX
0V
tRSTL
tRSTH
tR
tPDH
tPDL
RESISTOR
MASTER
DS2432
Read/Write Time Slots
The definitions of write and read time slots are illustrated in Figure 11. The master initiates all time slots
by driving the data line low. The falling edge of the data line synchronizes the DS2432 to the master by
triggering an internal delay circuit. During write time slots, the delay circuit determines when the DS2432
will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit
determines how long the DS2432 will hold the data line low. If the data bit is a “1”, the DS2432 will not
hold the data line low at all.
READ/WRITE TIMING DIAGRAM Figure 11
Write-one Time Slot
VPULLUP
VPULLUP MIN
VIH MIN
VIL MAX
0V
tLOW1
15 µs
(OD: 2 µs)
tSLOT
DS2432
Sampling Window
60 µs
(OD: 6 µs)
tREC
RESISTOR
MASTER
Write-zero Time Slot
VPULLUP
VPULLUP MIN
VIH MIN
VIL MAX
0V
tSLOT
DS2432
Sampling Window
15 µs
(OD: 2 µs)
tLOW0
60 µs
(OD: 6 µs)
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tREC
RESISTOR
MASTER

12 Page





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