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PDF DS2431-A1 Data sheet ( Hoja de datos )
| Número de pieza | DS2431-A1 | |
| Descripción | 1-Wire EEPROM | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Rev 1; 3/08
1024-Bit, 1-Wire EEPROM
for Automotive Applications
General Description
The DS2431-A1 is an AEC-Q100 Grade 1 qualified ver-
sion of the DS2431. The logical behavior of both ver-
sions is identical. The DS2431-A1 is a 1024-bit, 1-Wire®
EEPROM chip organized as four memory pages of 256
bits each. Data is written to an 8-byte scratchpad, veri-
fied, and then copied to the EEPROM memory. As a
special feature, the four memory pages can individually
be write protected or put in EPROM-emulation mode,
where bits can only be changed from a 1 to a 0 state.
The DS2431-A1 communicates over the single-conduc-
tor 1-Wire bus. The communication follows the standard
1-Wire protocol. Each device has its own unalterable
and unique 64-bit ROM registration number that is fac-
tory lasered into the chip. The registration number is
used to address the device in a multidrop 1-Wire net
environment.
Applications
Automotive Sensor Identification and Calibration
Data Storage
Automotive Cable Assembly Identification
Accessory/PCB Identification
Commands and modes are capitalized for clarity.
Typical Operating Circuit
Features
♦ 1024 Bits of EEPROM Memory Partitioned Into
Four Pages of 256 Bits
♦ Individual Memory Pages Can Be Permanently
Write Protected or Put in EPROM-Emulation Mode
(“Write to 0”)
♦ Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
♦ IEC 1000-4-2 Level 4 ESD Protection (+8kV
Contact, +15kV Air, Typ)
♦ Reads and Writes Over a 4.5V to 5.25V Voltage
Range from -40°C to +125°C
♦ Communicates to Host with a Single Digital
Signal at 15.4kbps Using 1-Wire Protocol
♦ Meets AEC-Q100 Grade 1 Qualification
Requirements
♦ Also Available as Standard Version for Industrial
Temperature Range (DS2431)
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
DS2431P-A1+
-40°C to +125°C 6 TSOC
DS2431P-A1+T -40°C to +125°C 6 TSOC
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Pin Configuration
VCC
μC
RPUP
I/O
DS2431-A1
GND
TOP VIEW
+
GND 1
I/O 2
N.C. 3
DS2431-A1
6 N.C.
5 N.C.
4 N.C.
TSOC
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
1024-Bit, 1-Wire EEPROM
for Automotive Applications
DS2431-A1 COMMAND LEVEL:
1-Wire ROM FUNCTION COMMANDS
(SEE FIGURE 9)
AVAILABLE COMMANDS:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
DATA FIELD AFFECTED:
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
RC-FLAG
RC-FLAG
DS2431-A1-SPECIFIC
MEMORY FUNCTION COMMANDS
(SEE FIGURE 7)
WRITE SCRATCHPAD
READ SCRATCHPAD
COPY SCRATCHPAD
READ MEMORY
Figure 2. Hierarchical Structure for 1-Wire Protocol
64-BIT SCRATCHPAD, FLAGS
64-BIT SCRATCHPAD
DATA MEMORY, REGISTER PAGE
DATA MEMORY, REGISTER PAGE
MSB
8-BIT
CRC CODE
MSB
LSB MSB
Figure 3. 64-Bit Lasered ROM
48-BIT SERIAL NUMBER
LSB
8-BIT FAMILY CODE
(2Dh)
LSB MSB
LSB
The hierarchical structure of the 1-Wire protocol is
shown in Figure 2. The bus master must first provide
one of the five ROM function commands: Read ROM,
Match ROM, Search ROM, Skip ROM, and Resume.
The protocol required for these ROM function com-
mands is described in Figure 9. After a ROM function
command is successfully executed, the memory func-
tions become accessible and the master can provide
any one of the four memory function commands. The
protocol for these memory function commands is
described in Figure 7. All data is read and written
least significant bit first.
64-Bit Lasered ROM
Each DS2431-A1 contains a unique ROM code that is 64
bits long. The first 8 bits are a 1-Wire family code. The
next 48 bits are a unique serial number. The last 8 bits
are a CRC (cyclic redundancy check) of the first 56 bits.
See Figure 3 for details. The 1-Wire CRC is generated
using a polynomial generator consisting of a shift regis-
ter and XOR gates as shown in Figure 4. The polynomial
is X8 + X5 + X4 + 1. Additional information about the
1-Wire CRC is available in Application Note 27.
The shift register bits are initialized to 0. Then, starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, the serial number is entered. After
the last bit of the serial number has been entered, the
shift register contains the CRC value. Shifting in the 8
bits of the CRC returns the shift register to all 0s.
_______________________________________________________________________________________ 5
5 Page 
1024-Bit, 1-Wire EEPROM
for Automotive Applications
Read Scratchpad [AAh]
The Read Scratchpad command allows verifying the
target address and the integrity of the scratchpad data.
After issuing the command code, the master begins
reading. The first two bytes are the target address. The
next byte is the ending offset/data status byte (E/S) fol-
lowed by the scratchpad data, which may be different
from what the master originally sent. This is of particular
importance if the target address is within the register
page or a page in either Write Protection or EPROM
modes. See the Write Scratchpad [0Fh] section for
details. The master should read through the scratchpad
(E2:E0 - T2:T0 + 1 bytes), after which it receives the
inverted CRC, based on data as it was sent by the
DS2431-A1. If the master continues reading after the
CRC, all data are logic 1s.
Copy Scratchpad [55h]
The Copy Scratchpad command is used to copy data
from the scratchpad to writable memory sections. After
issuing the Copy Scratchpad command, the master
must provide a 3-byte authorization pattern, which
should have been obtained by an immediately preced-
ing Read Scratchpad command. This 3-byte pattern
must exactly match the data contained in the three
address registers (TA1, TA2, E/S, in that order). If the
pattern matches, the target address is valid, the PF flag
is not set, and the target memory is not copy protected,
then the AA (authorization accepted) flag is set and the
copy begins. All eight bytes of scratchpad contents are
copied to the target memory location. The duration of
the device’s internal data transfer is tPROG during
which the voltage on the 1-Wire bus must not fall below
2.8V. A pattern of alternating 0s and 1s are transmitted
after the data has been copied until the master issues a
reset pulse. If the PF flag is set or the target memory is
copy protected, the copy does not begin and the AA
flag is not set.
Read Memory [F0h]
The Read Memory command is the general function to
read data from the DS2431-A1. After issuing the com-
mand, the master must provide the 2-byte target
address. After these two bytes, the master reads data
beginning from the target address and may continue
until address 008Fh. If the master continues reading,
the result is logic 1s. The device’s internal TA1, TA2,
E/S, and scratchpad contents are not affected by a
Read Memory command.
1-Wire Bus System
The 1-Wire bus is a system that has a single bus mas-
ter and one or more slaves. In all instances the
DS2431-A1 is a slave device. The bus master is typical-
ly a microcontroller. The discussion of this bus system
is broken down into three topics: hardware configura-
tion, transaction sequence, and 1-Wire signaling (signal
types and timing). The 1-Wire protocol defines bus
transactions in terms of the bus state during specific
time slots, which are initiated on the falling edge of
sync pulses from the bus master.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or
three-state outputs. The 1-Wire port of the DS2431-A1
is open drain with an internal circuit equivalent to that
shown in Figure 8.
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS2431-A1 communicates at a
maximum data rate of 15.4kbps. Note that legacy
1-Wire products support a standard communication
speed of 16.3kbps. The slightly reduced rates for the
DS2431-A1 are a result of additional recovery times,
which in turn were driven by a 1-Wire physical interface
enhancement to improve noise immunity. The value of
the pullup resistor primarily depends on the network
size and load conditions. The DS2431-A1 requires a
pullup resistor of 2.2kΩ (max).
The idle state for the 1-Wire bus is high. If for any rea-
son a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to
resume. If this does not occur and the bus is left low for
more than 120µs, one or more devices on the bus
might be reset.
Transaction Sequence
The protocol for accessing the DS2431-A1 through the
1-Wire port is as follows:
• Initialization
• ROM Function Command
• Memory Function Command
• Transaction/Data
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet DS2431-A1.PDF ] | |
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