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DS2476 Schematic ( PDF Datasheet ) - Maxim Integrated

Teilenummer DS2476
Beschreibung DeepCover Secure Coprocessor
Hersteller Maxim Integrated
Logo Maxim Integrated Logo 




Gesamt 8 Seiten
DS2476 Datasheet, Funktion
DS2476
ABRIDGED DATA SHEET
EVALUATION KIT AVAILABLE
DeepCover Secure Coprocessor
General Description
The DS2476 is a secure ECDSA and HMAC SHA-256
coprocessor companion to the DS28C36. The copro-
cessor can compute any required HMACs or ECDSA
signatures to do any operation on the DS28C36. The
DS2476 provides a core set of cryptographic tools derived
from integrated asymmetric (ECC-P256) and symmetric
(SHA-256) security functions. In addition to the security
services provided by the hardware implemented crypto
engines, the device integrates a FIPS/NIST true random
number generator (RNG), 8Kb of secured EEPROM, a
decrement-only counter, two pins of configurable GPIO,
and a unique 64-bit ROM identification number (ROM ID).
The ECC public/private key capabilities operate from
the NIST defined P-256 curve and include FIPS 186
compliant ECDSA signature generation and verification
to support a bidirectional asymmetric key authentication
model. The SHA-256 secret-key capabilities are compli-
ant with FIPS 180 and are flexibly used either in conjunc-
tion with ECDSA operations or independently for multiple
HMAC functions.
Two GPIO pins can be independently operated under
command control and include configurability supporting
authenticated and nonauthenticated operation including
an ECDSA-based crypto-robust mode to support secure-
boot of a host processor. This secure boot method can
also be used to enable the coprocessor functions.
DeepCover embedded security solutions cloak sensitive
data under multiple layers of advanced security to provide
the most secure key storage possible. To protect against
device-level security attacks, invasive and noninvasive
countermeasures are implemented including active die
shield, encrypted storage of keys, and algorithmic methods.
Applications
● IoT Node Crypto-Protection
● Accessory and Peripheral Secure Authentication
● Secure Storage of Cryptographic Keys for a Host
Controller
● Secure Boot or Download of Firmware and/or System
Parameters
Benefits and Features
● ECC-256 Compute Engine
FIPS 186 ECDSA P256 Signature and Verification
• ECDH Key Exchange with Authentication Prevents
Man-in-the-Middle Attacks
ECDSA Authenticated R/W of Configurable
Memory
● FIPS 180 SHA-256 Compute Engine
• HMAC
● SHA-256 OTP (One-Time Pad) Encrypted R/W of
Configurable Memory Through ECDH Established Key
● Two GPIO Pins with Optional Authentication Control
• Open-Drain, 4mA/0.4V
• Optional SHA-256 or ECDSA Authenticated On/Off
and State Read
Optional ECDSA Certificate to Set On/Off after
Multiblock Hash for Secure Boot
● RNG with NIST SP 800-90B Compliant Entropy
Source with Function to Read Out
● Optional Chip Generated Pr/Pu Key Pairs for ECC
Operations
● 17-Bit One-Time Settable, Nonvolatile Decrement-
Only Counter with Authenticated Read
● 8Kbits of EEPROM for User Data, Keys, and
Certificates
● Unique and Unalterable Factory Programmed 64-Bit
Identification Number (ROM ID)
• Optional Input Data Component to Crypto and Key
Operations
● I2C Communication, 100kHz and 400kHz
● Operating Range: 3.3V ±10%, -40°C to +85°C
● 6-Pin TDFN Package
Ordering Information appears at end of data sheet.
Typical Application Circuit appears at end of data sheet.
19-8589; Rev 0; 7/16






DS2476 Datasheet, Funktion
DS2476
ABRIDGED DATA SHEET
DeepCover Secure Coprocessor
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers. The timing references are defined in
Figure 43.
Bus Idle or Not Busy
Both SDA and SCL are inactive and in their logic-high
states.
START Condition
To initiate communication with a slave, the master must
generate a START condition. A START condition is
defined as a change in state of SDA from high to low while
SCL remains high.
STOP Condition
To end communication with a slave, the master must
generate a STOP condition. A STOP condition is defined
as a change in state of SDA from low to high while SCL
remains high.
Repeated START Condition
Repeated STARTs are commonly used for read accesses
after having specified a memory address to read from in
a preceding write access. The master can use a repeated
START condition at the end of a data transfer to immedi-
ately initiate a new data transfer following the current one.
A repeated START condition is generated the same way
as a normal START condition, but without leaving the bus
idle after a STOP condition.
Data Valid
With the exception of the START and STOP condition,
transitions of SDA can occur only during the low state of
SCL. The data on SDA must remain valid and unchanged
during the entire high pulse of SCL plus the required
setup and hold time (tHD:DAT after the falling edge of SCL
and tSU:DAT before the rising edge of SCL; see Figure
43). There is one clock pulse per bit of data. Data is
shifted into the receiving device during the rising edge of
the SCL pulse.
When finished with writing, the master must release the
SDA line for a sufficient amount of setup time (minimum
tSU:DAT + tR in Figure 43) before the next rising edge of
SCL to start reading. The slave shifts out each data bit
on SDA at the falling edge of the previous SCL pulse and
the data bit is valid at the rising edge of the current SCL
pulse. The master generates all SCL clock pulses, includ-
ing those needed to read from a slave.
SDA
tBUF
SCL
tLOW
tHD:STA tR
STOP START
Figure 43: I2C Timing Diagram
tF
tHD:STA
tSP
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
REPEATED
START
SPIKE
SUPPRESSION
tSU:STO
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