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853S111B Schematic ( PDF Datasheet ) - IDT

Teilenummer 853S111B
Beschreibung LVPECL/ECL Fanout Buffer
Hersteller IDT
Logo IDT Logo 




Gesamt 25 Seiten
853S111B Datasheet, Funktion
Low Skew, 1-to-10, Differential-to-2.5V,
3.3V LVPECL/ECL Fanout Buffer
853S111B
DATA SHEET
General Description
The 853S111B is a low skew, high performance 1-to-10
Differential-to-2.5V/ 3.3V LVPECL/ECL Fanout Buffer. The
853S111B is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the 853S111B ideal for those clock distribution
applications demanding well defined performance and repeatability.
Pin Assignments
VCCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
VCCO
24 23 22 21 20 19 18 17
25 16
26 853S111B 15
27 32-Lead TQFP, E-Pad 14
28 7mm x 7mm x 1mm 13
29 package body 12
30 Y Package 11
31 Top View 10
32 9
12 3 45 6 78
VCCO
Q7
nQ7
Q8
nQ8
Q9
nQ9
VCCO
VCCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
VCCO
24 23 22 21 20 19 18 17
25 16
26 853S111B 15
27 32-Lead VFQFN 14
28 5mm x 5mm x 0.925mm 13
29 package body 12
30 K Package 11
31 Top View 10
32 9
12 3 45 6 78
VCCO
Q7
nQ7
Q8
nQ8
Q9
nQ9
VCCO
Features
Ten differential 2.5V, 3.3V LVPECL/ECL outputs
Two selectable differential input pairs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, SSTL, CML
Maximum output frequency: 2.5GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
Output skew: 50ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 645ps (maximum)
Additive Phase Jitter, RMS: 0.03ps (typical)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
-40°C to 85°C ambient operating temperature
Available lead-free (RoHS 6) packaging
Block Diagram
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
CLK_SEL Pulldown
VBB
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
nQ3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
nQ8
nQ8
Q9
nQ9
853S111B REVISION E 6/30/15
1 ©2015 Integrated Device Technology, Inc.






853S111B Datasheet, Funktion
853S111B DATA SHEET
Table 4C. LVPECL DC Characteristics, VCC = VCCO = 2.5V; VEE = 0V, TA = -40°C to 85°C
-40°C
25°C
Symbol Parameter
Min Typ Max Min Typ Max
VOH Output High Voltage; NOTE 1
1.375 1.475 1.645 1.425 1.495 1.645
VOL Output Low Voltage; NOTE 1
0.605 0.745 0.90 0.575 0.72 0.845
VIH Input High Voltage (Single-ended) 1.275
1.56 1.275
1.56
VIL
Input Low Voltage (Single-ended)
0.63
0.965 0.63
0.965
VBB Output Voltage Reference
0.87
1.34 0.87
1.34
VPP
Peak-to-Peak Input Voltage;
NOTE 2
150 800 1300 150 800 1200
VCMR1
Input High Voltage Common Mode
Range; NOTE 2, 3
1.3
2.5 1.2
2.5
VCMR2
Input Voltage Common Mode Range
referenced to Cross-point; NOTE 2,
4
1.3 -
VPP/2
2.5 - 1.2 -
VPP/2 VPP/2
2.5 -
VPP/2
IIH
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
200 200
IIL
Input
PCLK0, PCLK1
Low Current nPCLK0, nPCLK1
-10
-200
-10
-200
Min
1.415
0.555
1.275
0.63
0.87
150
1.2
1.2 -
VPP/2
-10
-200
85°C
Typ
1.53
0.735
800
Max
1.61
0.83
1.56
0.965
1.34
1200
2.5
2.5 -
VPP/2
200
Units
V
V
V
V
V
mV
V
V
µA
µA
µA
NOTE: Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50to VCCO – 2V.
NOTE 2: VIL should not be less than VEE – 0.3V, VIH should not be greater than VCC.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: Common mode voltage is defined as VCROSS-POINT.
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL
FANOUT BUFFER
6
REVISION E 6/30/15

6 Page









853S111B pdf, datenblatt
853S111B DATA SHEET
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both differential signals must meet the VPP and
VCMR input requirements. Figures 2A to 2F show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3 R4
120 120
3.3V
PCLK
R1 R2
120 120
nPCLK
LVPECL
Input
3.3V
Zo = 50Ω
LVDS
Zo = 50Ω
R5
100Ω
3.3V
C1
C2
R1 R2
1k 1k
PCLK
VBB
nPCLK
LVPECL
Input
C3
0.1µF
Figure 2A. PCLK/nPCLK Input Driven by an SSTL Driver
Figure 2B. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
PCLK
nPCLK
LVPECL
R1 R2
84Ω 84Ω
Input
3.3V
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
R5 R6
100Ω - 200Ω 100Ω - 200Ω
3.3V
C1
PCLK
C2 VBB
nPCLK
LVPECL
R1 R2
50Ω 50Ω
Input
Figure 2C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1 R2
50Ω 50Ω
3.3V
PCLK
nPCLK
LVPECL
Input
3.3V
Zo = 50Ω
CML Built-In Pullup
Zo = 50Ω
R1
100Ω
3.3V
PCLK
nPCLK
LVPECL
Input
Figure 2E. PCLK/nPCLK Input Driven by a CML Driver
Figure 2F. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL
FANOUT BUFFER
12
REVISION E 6/30/15

12 Page





SeitenGesamt 25 Seiten
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