|
|
PDF 8413S12B Data sheet ( Hoja de datos )
| Número de pieza | 8413S12B | |
| Descripción | HCSL/ LVCMOS Clock Generator | |
| Fabricantes | IDT | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 8413S12B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
HCSL/ LVCMOS Clock Generator
8413S12B
General Description
The 8413S12B is a PLL-based clock generator. This high
performance device is optimized to generate the processor core
reference clock, the PCI-Express, sRIO, XAUI, SerDes reference
clocks and the clocks for both the Gigabit Ethernet MAC and PHY.
The clock generator offers ultra low-jitter, low-skew clock outputs.
The output frequencies are generated from a 25MHz external input
source or an external 25MHz parallel resonant crystal. The industrial
temperature range of the 8413S12B supports telecommunication,
networking, and storage requirements.
Applications
• CPE Gateway Design
• Home Media Servers
• 802.11n AP or Gateway
• Soho Secure Gateway
• Soho SME Gateway
• Wireless Soho and SME VPN Solutions
• Wired and Wireless Network Security
• Web Servers and Exchange Servers
Pin Assignment
Features
• Ten selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz
clocks for PCI Express, sRIO and GbE, HCSL interface levels
• One single-ended QG LVCMOS/LVTTL clock output at 125MHz
• One single-ended QF LVCMOS/LVTTL clock output at 50MHz,
15 output impedance
• Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz,
15 output impedance
• Selectable external crystal or differential (single-ended) input
source
• Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
• Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
• Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
• Supply Modes, (125MHz QG output and 25MHz QREFx outputs):
Core / Output
3.3V / 3.3V
3.3V / 2.5V
• Supply Modes, (HCSL outputs, and 50MHz QF output):
Core / Output
3.3V / 3.3V
• -40°C to 85°C ambient operating temperature
• Available in Lead-free (RoHS 6) package
GND
FSEL_A0
FSEL_A1
FSEL_B0
FSEL_B1
FSEL_C0
FSEL_C1
FSEL_D0
FSEL_D1
FSEL_E0
VDDA
FSEL_E1
nc
XTAL_IN
XTAL_OUT
nc
REF_SEL
GND
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1 54
2 53
3 52
4 51
5 50
6 ;;;;;;
7
49
48
8 47
9
10
6
46
45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
nc
VDD
IREF
OE_D
nQD1
QD1
nQD0
QD0
VDDO_D
VDDO_C
nQC1
QC1
nQC0
QC0
OE_C
VDD
GND
nc
SLQPP[PP/4)33DFNDJH
©2016 Integrated Device Technology, Inc.
1
Revision E, August 18, 2016
1 page  
Function Tables
Table 3A. FSEL_X Control Input Function Table
Input
Output Frequency
FSEL_X[0:1]
Q[Ax:Ex], nQ[Ax:Ex]
00 (default)
100MHz
01 125MHz
10 156.25MHz
11 312.50MHz
NOTE: FSEL_X denotes FSEL_A, _B, _C, _D, _E.
NOTE Any two outputs operated at the same frequency will be
synchronous.
Table 3B. PLL_SEL Control Input Function Table
Input
PLL_SEL
Operation
0 PLL Bypass
1 (default)
PLL Mode
Table 3C. REF_SEL Control Input Function Table
Input
REF_SEL
Clock Source
0 CLK, nCLK
1 (default)
XTAL_IN, XTAL_OUT
8413S12B Datasheet.
Table 3D. OE_[A:E] Control Input Function Table
Input
Outputs
OE_[A:E]
Q[Ax:Ex], nQ[Ax:Ex]
0 High-Impedance
1 (default)
Enabled
Table 3E. OE_G Control Input Function Table
Input
Outputs
OE_G
QG
0 High-Impedance
1 (default)
Enabled
Table 3F. OE_REF Control Input Function Table
Input
Output
OE_REF
QREF[0:1]
0 High-Impedance
1 (default)
Enabled
©2016 Integrated Device Technology, Inc.
5
Revision E, August 18, 2016
5 Page 
8413S12B Datasheet.
Table 7G. HCSL AC Characteristics, VDD = 3.3V ± 5%, VDDO_[A:E] = VDDO_F = 3.3V ± 5%; and
VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Output Configurations
Outputs
Minimum Typical
RJ Random Jitter
QA = QD = 100MHz,
QB = QG = 125MHz,
QC = QE = 156.25MHz,
QF = 50MHz,
QREF0 = QREF1 = 25MHz
QA, nQA
QB, nQB
QC, nQC
QD, nQD
QE, nQE
3
3
3
3
3
DJ Deterministic Jitter
QA = QD = 100MHz,
QB = QG = 125MHz,
QC = QE = 156.25MHz,
QF = 50MHz,
QREF0 = QREF1 = 25MHz
QA, nQA
QB, nQB
QC, nQC
QD, nQD
QE, nQE
20
43
64
30
70
RMS Phase Jitter, (Random)
Integration Range:
(10kHz to 1.5MHz)
QA, nQA;
QD, nQD
0.66
tjit(Ø)
RMS Phase Jitter, (Random)
Integration Range:
(1.5MHz to 50MHz)
RMS Phase Jitter, (Random)
Integration Range:
(20MHz to 78.125MHz)
QA = QD = 100MHz,
QB = QG = 125MHz,
QC = QE = 156.25MHz,
QF = 50MHz,
QREF0 = QREF1 = 25MHz
QA, nQA;
QD, nQD
QC, nQC;
QE, nQE
0.56
0.34
RMS Phase Jitter, (Random)
Integration Range:
(12kHz to 50MHz)
QC, nQC;
QE, nQE
0.85
Maximum
5
5
5
5
5
50
100
100
80
120
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
0.76 ps
0.68 ps
0.48 ps
0.95 ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: Refer to Applications Section for peak-to-peak jitter calculations.
©2016 Integrated Device Technology, Inc.
11
Revision E, August 18, 2016
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 8413S12B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 8413S12 | HCSL/ LVCMOS Clock Generator | IDT |
| 8413S12B | HCSL/ LVCMOS Clock Generator | IDT |
| 8413S12I-100 | Clock Generator | IDT |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |