Datenblatt-pdf.com

8413S12B Schematic ( Datenblatt PDF ) - IDT

Teilenummer 8413S12B
Beschreibung HCSL/ LVCMOS Clock Generator
Hersteller IDT
Logo IDT Logo 

Gesamt 30 Seiten
		
8413S12B Datasheet, Funktion
HCSL/ LVCMOS Clock Generator
8413S12B
General Description
The 8413S12B is a PLL-based clock generator. This high
performance device is optimized to generate the processor core
reference clock, the PCI-Express, sRIO, XAUI, SerDes reference
clocks and the clocks for both the Gigabit Ethernet MAC and PHY.
The clock generator offers ultra low-jitter, low-skew clock outputs.
The output frequencies are generated from a 25MHz external input
source or an external 25MHz parallel resonant crystal. The industrial
temperature range of the 8413S12B supports telecommunication,
networking, and storage requirements.
Applications
CPE Gateway Design
Home Media Servers
802.11n AP or Gateway
Soho Secure Gateway
Soho SME Gateway
Wireless Soho and SME VPN Solutions
Wired and Wireless Network Security
Web Servers and Exchange Servers
Pin Assignment
Features
Ten selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz
clocks for PCI Express, sRIO and GbE, HCSL interface levels
One single-ended QG LVCMOS/LVTTL clock output at 125MHz
One single-ended QF LVCMOS/LVTTL clock output at 50MHz,
15output impedance
Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz,
15output impedance
Selectable external crystal or differential (single-ended) input
source
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Supply Modes, (125MHz QG output and 25MHz QREFx outputs):
Core / Output
3.3V / 3.3V
3.3V / 2.5V
Supply Modes, (HCSL outputs, and 50MHz QF output):
Core / Output
3.3V / 3.3V
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
GND
FSEL_A0
FSEL_A1
FSEL_B0
FSEL_B1
FSEL_C0
FSEL_C1
FSEL_D0
FSEL_D1
FSEL_E0
VDDA
FSEL_E1
nc
XTAL_IN
XTAL_OUT
nc
REF_SEL
GND
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1 54
2 53
3 52
4 51
5 50
6 ;;;;;;
7
49
48
8 47
9
10
6
46
45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
nc
VDD
IREF
OE_D
nQD1
QD1
nQD0
QD0
VDDO_D
VDDO_C
nQC1
QC1
nQC0
QC0
OE_C
VDD
GND
nc
SLQPP[PP/4)33DFNDJH
©2016 Integrated Device Technology, Inc.
1
Revision E, August 18, 2016






8413S12B Datasheet, Funktion
8413S12B Datasheet.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, VDD
Inputs, VI
XTAL_IN
Other Inputs
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
Rating
4.6V
0V to VDD
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
25.4°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
VDD = 3.3V ± 5%, VDDO_[A:E] = VDDO_[F:G] = VDDO_QREF = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
VDD
VDDA
VDDO_X
IDD
IDDA
IDDO_X
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.135
VDD – 0.16
3.135
No Load, CLK selected
NOTE: VDDO_X denotes VDDO_[A:E], VDDO_[F:G}, VDDO_QREF.
NOTE: IDDO_X denotes IDDO_[A:E] + IDDO_[F:G] + IDDO_QREF
Typical
3.3
3.3
3.3
86
13
76
Maximum
3.465
VDD
3.465
103
16
91
Units
V
V
V
mA
mA
mA
Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
VDDA
VDDO_X
IDD
IDDA
IDDO_X
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load, CLK selected
3.135
VDD – 0.16
2.375
3.3
3.3
2.5
79
13
50
3.465
VDD
2.625
95
16
60
V
V
V
mA
mA
mA
NOTE: VDDO_X denotes VDDO_G, VDDO_QREF.
NOTE: IDDO_X denotes IDDO_G + IDDO_QREF.
©2016 Integrated Device Technology, Inc
6
Revision E, August 18, 2016

6 Page







8413S12B pdf, datenblatt
8413S12B Datasheet.
Table 7H. AC Characteristics, VDD = 3.3V ± 5%, VDDO_[A:E] = VDDO_F = 3.3V ± 5%; and
VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VRB
Ring-Back Voltage Margin;
NOTE 1, 2
Q[A:E],
nQ[A:E]
-100
tSTABLE
Time before VRB is allowed;
NOTE 1, 2
Q[A:E],
nQ[A:E]
500
VMAX
Absolute Max Output Voltage; Q[A:E],
NOTE 3, 4
nQ[A:E]
VMIN
Absolute Min Output Voltage; Q[A:E],
NOTE 3, 5
nQ[A:E]
-300
VCROSS
Absolute Crossing Voltage;
NOTE 3, 6, 7
Q[A:E],
nQ[A:E]
250
VCROS
S
tSLEW+
Total Variation of VCROSS over
All Edges; NOTE 3, 6, 8
Rising Edge Rate; NOTE 1, 9
Q[A:E],
nQ[A:E]
Q[A:E],
nQ[A:E]
0.6
tSLEW-
Falling Edge Rate; NOTE 1, 9
Q[A:E],
nQ[A:E]
0.6
odc Output Duty Cycle
Q[A:E],
nQ[A:E]
48
tjit(Ø)
RMS Phase Jitter, (Random) QREF[0:1]
25MHz, Integration Range:
(10kHz to 5MHz)
QF
20% to 80%
400
tR /tF
Output Rise/Fall Time
QG
QREF[0:1]
20% to 80%
20% to 80%
400
300
odc Output Duty Cycle
QF
QG
QREF[0:1]
measured at VDDO_F/2
measured at VDDO_G/2
measured at VDDO_QREF/2
48
45
45
Typical
0.6
50
50
50
Maximum Units
100 mV
ps
1150
mV
mV
550 mV
140 mV
5.5 V/ns
5.5 V/ns
52 %
0.96
1400
1400
1400
52
55
55
ps
ps
ps
ps
%
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: All parameters measured at fOUT unless noted otherwise.
NOTE 1: Measurement taken from differential waveform.
NOTE 2: tSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the Vrb ±100mV range. See Parameter Measurement Information Section.
NOTE 3: Measurement taken from single-ended waveform.
NOTE 4: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 5: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 6: Measured at the crossing point where the instantaneous voltage value of the rising edge of Q[Ax:Ex] equals the falling edge of
nQ[Ax:Ex].
NOTE 7: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
NOTE 8: Defined as the total variation of all crossing voltages of rising Q[Ax:Ex] and falling nQ[Ax:Ex]. This is the maximum allowed variance
in Vcross for any particular system.
NOTES continued on next page.
NOTE 9: Measured from -150mV to +150mV on the differential waveform (derived from Q[Ax:Ex] minus nQ[Ax:Ex]). The signal must be
monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero
crossing.
©2016 Integrated Device Technology, Inc
12
Revision E, August 18, 2016

12 Page


SeitenGesamt 30 Seiten
PDF Download[ 8413S12B.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
8413S12HCSL/ LVCMOS Clock GeneratorIDT
IDT
8413S12BHCSL/ LVCMOS Clock GeneratorIDT
IDT
8413S12I-100Clock GeneratorIDT
IDT

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com    |   2018   |  Kontakt  |   Suche