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CD40107BMS Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer CD40107BMS
Beschreibung CMOS Dual 2 Input NAND Buffer/Driver
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 7 Seiten
CD40107BMS Datasheet, Funktion
CD40107BMS
December 1992
CMOS Dual 2 Input NAND Buffer/Driver
Features
Pinouts
• High Voltage Type (20V Rating)
• 32 Times Standard B Series Output Current Drive
Sinking Capability
- 136mA Typ. at VDD = 10V
- VDS = 1V
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
RL to VDD = 10k
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
CD40107BF
TOP VIEW
NC 1
NC 2
A3
B4
C=A• B 5
NC 6
VSS 7
14 VDD
13 NC
12 NC
11 D
10 E
9 F=D• E
8 NC
NC = NO CONNECTION
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Functional Diagram
Applications
• Driving Relays, Lamps, LEDs
• Line Driver
• Level Shifter (Up or Down)
C=A• B
A
B
VSS
Description
F=D• E
CD40107BMS is a dual 2 input NAND buffer/driver contain-
D
E
ing two independent 2 input NAND buffers with open drain
single n-channel transistor outputs. This device features a
VSS
wired OR capability and high output sink current capability
(136mA typ. at VDD = 10V, VDS = 1V).
The CD40107BMS is supplied in these 14 lead outline
packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4H
H1B
H3W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-18
File Number 3355






CD40107BMS Datasheet, Funktion
Schematic
A*
3, (11)
B*
4, (10)
VDD
NOTE:
VSS
1 OF 2 GATES (NUMBERS IN PARENTHESES
ARE TERMINAL NUMBERS FOR SECOND GATE)
CD40107BMS
VDD
* ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
C=A• B
5, (9)
VSS
VDD = 14
VSS = 7
TRUTH TABLE
AB
C
0 0 1* Z**
1 0 1* Z**
0 1 1* Z**
110
* Requires external pull-up resistor (RL)
to VDD.
** Without pull-up resistor (3-state).
FIGURE 1. 1 OF 2 GATES
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
960 GATE-TO-SOURCE VOLTAGE (VGS) = 15V
800
640
480 10V
320
160 5V
0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
80
AMBIENT TEMPERATURE (TA) = +25oC
70 RL = 120TO VDD
60 SUPPLY VOLTAGE (VDD) = 5V tTLH
50 5V tTHL
40
30
20
10
10V tTLH
15V tTLH
10V tTHL
15V tTHL
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (CL) (pF)
FIGURE 4. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
480
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
400
320
10V
240
160
80 5V
0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
175 RL = 120TO VDD
150
125 SUPPLY VOLTAGE (VDD) = 5V tPLH, tPHL
100
75
15V tPLH
50
25
10V tPHL
10V tPLH
10V TPHL
15V tPHL
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (CL) (pF)
FIGURE 5. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
7-23

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