|
|
PDF AD9721 Data sheet ( Hoja de datos )
| Número de pieza | AD9721 | |
| Descripción | D/A Converters | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9721 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
|
No Preview Available !
a
10-Bit, 400 MSPS
D/A Converters
AD9720/AD9721
FEATURES
lated bipolar process. The AD9720 is ECL compatible, and will
400 MSPS (ECL)/100 MSPS (TTL) Update Rate
update up to 400 MSPS; the AD9721 is TTL compatible and
Low Glitch Impulse: 1.5 pV-s
will update up to 100 MSPS.
Fast Settling: 4.5 ns to 1/2 LSB
Low Power: 1.1 W
On-Board Quadrature Logic for DDS Applications
Differential Clock (ECL)
Designed for direct digital synthesis (DDS), waveform recon-
struction, and high resolution video applications, both devices
feature low glitch impulse of 1.5 pV-s and fast settling times of
4.5 ns to 1/2 LSB.
APPLICATIONS
Direct Digital Synthesis
Arbitrary Waveform Synthesis
Waveform Reconstruction
High Speed Imaging
OGENERAL DESCRIPTION
BThe AD9720 and AD9721 D/A converters are 10-bit, high
speed digital-to-analog converters constructed in an oxide iso-
Both converters are characterized for dynamic performance, and
have excellent harmonic suppression and spectral purity in
waveform generation applications.
The units are available in 28-pin DIPs, LCCs and SOICs.
Industrial temperature range devices are packaged in plastic for
operation from –25°C to +25°C; extended temperature range
devices for operation from –55°C to +125°C are in hermetic
ceramic packages. Contact the factory for information about the
availability of MIL-STD-883 devices.
SOLD1
ED2
TETTL
FUNCTIONAL BLOCK DIAGRAM
10
ANALOG
RETURN
IOUT
OR IOUT
ECL
DRIVE
D10
LOGIC
INVERT
CLOCK
CLOCK
REFERENCE
IN
INTERNAL
VOLTAGE
REFERENCE
+
CONTROL
AMP
–
CONTROL
AMP OUT
0.1µF
RSET
REFERENCE
OUT
CONTROL
AMP IN
DIGITAL
–V S
DIGITAL
+VS
ANALOG
–V S
–5.2V
BYP.
+5V
BYP.
–5.2V
BYP.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD9720/AD9721
CLOCK
CLOCK
CLOCK
DATA INPUTS CODE 1
D1 – D10
VALID DATA
tS tH
CODE 2
VALID DATA
CLOCK
OUTPUT
ERROR
ERROR
BAND
t PD tST
OUTPUT
CODE 1
tPD
CODE 2
tS – INPUT SETUP TIME
tH – INPUT HOLD TIME
tST – OUTPUT SETTLING TIME
tPD – OUTPUT PROPAGATION DELAY
AD9720/AD9721 Timing Diagram
THEORY AND APPLICATIONS
The AD9720/AD9721 high speed digital-to-analog converters
utilize Most Significant Bit (MSB) decoding and segmentation
Otechniques to reduce glitch impulse and maintain 10-bit linear-
ity without trimming.
BAs shown in the functional block diagram, the design is based
Son four main subsections: the Decoder/Driver circuits, the Edge
Triggered Data Register, the Switch Network, and the Control
OAmplifier. An internal bandgap reference is also included to al-
Llow operation with a minimum of external components. The
block labeled “Inverters” is transparent in normal operation, but
Ecan be used to minimize the external components requirements
Tin DDS applications using the AD9950, a 300 MSPS phase ac-
Ecumulator (see AD9950 data sheet).
When using the internal reference, REFERENCE OUT (Pin
25) should be connected to CONTROL AMP IN (Pin 26).
CONTROL AMP OUT (Pin 24) should be connected to REF-
ERENCE IN (Pin 23). A 0.1 µF ceramic capacitor from Pin 23
to ANALOG –VS (Pin 22) improves settling by decoupling
switching noise from the current sink base line. A reference
current cell provides feedback to the control amp by sinking
current through RSET (Pin 17).
Full-scale output current is determined by CONTROL AMP IN
and RSET according to the equation:
IOUT (FS) = (CONTROL AMP IN/RSET) ϫ 32
The internal reference is nominally –1.25 V with a tolerance of
± 8% and typical drift over temperature of 100 ppm/°C. If
greater accuracy or better temperature stability is required, an
Digital Inputs/Timing
external reference can be utilized. The AD589 reference features
The AD9720 employs single-ended ECL-compatible inputs for ± 10 ppm/°C drift over temperatures from 0°C to +70°C.
data inputs D1–D10 and the differential clock signals CLOCK
and CLOCK. The internal ECL midpoint reference is designed Two modes of multiplying operation are possible with the
to match 10K ECL device thresholds. On the AD9721, a TTL
AD9720/AD9721. Signals with bandwidths up to 1 MHz and
translator is added at each input and the clock becomes single
input swings from –0.6 V to –1.2 V can be applied to the CON-
ended; with these exceptions, the AD9720 and AD9721 are
TROL AMP input as shown in Figure 1. Because the control
identical. (NOTE: Pin 14 is +VS on AD9721; –VS on AD9720.) amplifier is internally compensated, the 0.1 µF capacitor dis-
cussed above can be reduced to maximize the multiplying band-
In the Decoder/Driver section, the four MSBs (D1–D4) are de-
width. However, it should be noted that settling time for
coded to 15 “thermometer code” lines. An equalizing delay is
changes to the digital inputs will be degraded.
included for the six Least Significant Bits (LSBs) and the clock
signals. This delay minimizes data skew and data setup and hold
times at the register inputs.
AD9720/AD9721
The on-board register is rising-edge-triggered and should be
used to synchronize data to the current switches by applying a
RSET
17 RSET
pulse with proper data set-up and hold times as shown in the
timing diagram.
Although the AD9720/AD9721 chip is designed to provide iso-
lation from digital inputs to the outputs, some coupling of digi-
–0.6V TO –1.2V
400 kHz MAX
26
CONTROL
AMP IN
RT
tal transitions is inevitable, especially with TTL or CMOS
inputs applied to the AD9721. Digital feedthrough can be re-
duced by forming a low-pass filter using a resistor in series with
24
CONTROL
AMP OUT
the capacitance of each digital input; this rolls off the slew rate
of the digital inputs.
References
As shown in the functional block diagram, the internal band-gap
reference, control amplifier, and reference input are pinned out
0.1µF
23
REFERENCE
IN
ANALOG – VS
for maximum user flexibility when setting the reference.
Figure 1. Low Frequency Multiplying Circuit
REV. A
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AD9721.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9720 | D/A Converters | Analog Devices |
| AD9721 | D/A Converters | Analog Devices |
| AD9725 | 14-Bit/ 600+ MSPS D/A Converter | Analog Devices |
| AD9726 | Digital-to-Analog Converter | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |