CD40104BMS Datasheet PDF - Intersil Corporation
| Part Number | CD40104BMS | |
| Description | CMOS 4-Bit Bidirectional Universal Shift Register | |
| Manufacturers | Intersil Corporation | |
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December 1992
CD40104BMS,
CD40194BMS
CMOS 4-Bit Bidirectional
Universal Shift Register
Features
• High Voltage Type (20V Rating)
• Medium Speed fCL = 12MHz (typ.) at VDD = 10V
• Fully Static Operation
• Synchronous Parallel or Serial Operation
• Three State Outputs (CD40104BMS)
• Asynchronous Master Reset (CD40194BMS)
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Arithmetic Unit Bus Registers
• Serial/Parallel Conversions
• General Purpose Register for Bus Organized Systems
• General Purpose Registers
Description
The CD40104BMS is a universal shift register featuring parallel
inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial
inputs, and a high impedance third output state allowing the device
to be used in bus organized systems.
In the parallel load mode (S0 and S1 are high), data is loaded into
the associated flip-flop and appears at the output after the positive
transition of the CLOCK input. During loading, serial data flow is
inhibited. Shift right and shift left are accomplished synchronously
on the positive clock edge with serial data entered at the SHIFT
RIGHT and SHIFT LEFT serial inputs, respectively. Clearing the
register is accomplished by setting both mode controls low and
clocking the register. When the output enable input is low, all outputs
assume the high impedance state.
The CD40194BMS is a universal shift register featuring parallel inputs,
parallel outputs SHIFT RIGHT and SHIFT LEFT serial inputs, and a
direct overriding clear input. In the parallel load mode (S0 and S1 are
high), data is loaded into the associated flip-flop and appears at the out-
put after the positive transition of the CLOCK input. During loading,
serial data flow is inhibited. Shift right and shift left are accomplished
synchronously on the positive clock edge with data entered at the
SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clocking of
the register is inhibited when both mode control inputs are low. When
low, the RESET input resets all stages and forces all outputs low. The
CD40194BMS is similar to industry types 340194 and MC40194.
The CD40104BMS and CD40194BMS series types are supplied in
these 16 lead outline packages
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
* CD40104B Only
*HNX, †H4W
*H1L, †HIF
H6W
†CD40194B Only
Pinouts
CD40104BMS
TOP VIEW
OUTPUT ENABLE 1
SHIFT RIGHT IN 2
D0 3
D1 4
D2 5
D3 6
SHIFT LEVEL IN 7
VSS 8
16 VDD
15 Q0
14 Q1
13 Q2
12 Q3
11 CLOCK
10 SELECT 1
9 SELECT 0
CD40194BMS
TOP VIEW
RESET 1
SHIFT RIGHT IN 2
D0 3
D1 4
D2 5
D3 6
SHIFT LEVEL IN 7
VSS 8
16 VDD
15 Q0
14 Q1
13 Q2
12 Q3
11 CLOCK
10 SELECT 1
9 SELECT 0
Functional Diagrams
CD40104BMS
OUTPUT ENABLE
3
D0
4
D1
D2 5
D3 6
7
SHIFT LEFT IN
2
SHIFT RIGHT IN 9
S0
MODE SELECT S1 10
CLOCK
1
11
15
Q0
14
Q1
13 Q2
12 Q3
VDD = 16
VSS = 8
CD40194BMS
RESET
3
D0
4
D1
5
D2
D3 6
7
SHIFT LEFT IN 2
SHIFT RIGHT IN 9
S0
MODE SELECT
10
S1
CLOCK
1
11
15
Q0
14
Q1
13
Q2
12 Q3
VDD = 16
VSS = 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1307
File Number 3352
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Specifications CD40104BMS, CD40194BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Minimum Reset Pulse
Width CD40194BMS
Input Capacitance
SYMBOL
CONDITIONS
TW VDD = 5V
VDD = 10V
VDD = 15V
CIN Any Input
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
+25oC
+25oC
+25oC
+25oC
MIN
-
-
-
-
MAX
300
200
140
7.5
UNITS
ns
ns
ns
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
N Threshold Voltage
VNTH VDD = 10V, ISS = -10µA
N Threshold Voltage
Delta
∆VTN VDD = 10V, ISS = -10µA
P Threshold Voltage
VTP VSS = 0V, IDD = 10µA
P Threshold Voltage
Delta
∆VTP VSS = 0V, IDD = 10µA
Functional
F VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL VDD = 5V
TPLH
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
NOTES
1, 4
1, 4
1, 4
TEMPERATURE
+25oC
+25oC
+25oC
MIN
-
-2.8
-
1, 4
+25oC
0.2
1, 4
+25oC
-
1
1, 2, 3, 4
+25oC
+25oC
VOH >
VDD/2
-
3. See Table 2 for +25oC limit.
4. Read and Record
MAX
25
-0.2
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25oC
Limit
UNITS
µA
V
V
V
V
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD ± 1.0µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
Output Current (Source)
IOH5A
± 20% x Pre-Test Reading
7-1311
Preview 5 Page |
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