PDF EM68C08CWAG Data sheet ( Hoja de datos )

Número de pieza	EM68C08CWAG
Descripción	128M x 8 bit DDRII Synchronous DRAM
Fabricantes	Etron Technology
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EtronTech EM68C08CWAG 128M x 8 bit DDRII Synchronous DRAM (SDRAM) Advance (Rev. 1.1, Apr. /2016) Features  JEDEC Standard Compliant  JEDEC standard 1.8V I/O (SSTL_18-compatible)  Power supplies: VDD & VDDQ = +1.8V  0.1V  Operating temperature: TC = 0~85 °C  Supports JEDEC clock jitter specification  Fully synchronous operation  Fast clock rate: 333/400/533 MHz  Differential Clock, CK & CK#  Bidirectional single/differential data strobe  8 internal banks for concurrent operation  4-bit prefetch architecture  Internal pipeline architecture  Precharge & active power down  Programmable Mode & Extended Mode registers  Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5, 6  WRITE latency = READ latency - 1 tCK  Burst lengths: 4 or 8  Burst type: Sequential / Interleave  DLL enable/disable  Off-Chip Driver (OCD) - Impedance Adjustment - Adjustable data-output drive strength  On-die termination (ODT)  RoHS compliant  Auto Refresh and Self Refresh  8192 refresh cycles / 64ms  60-ball 8 x 10 x 1.2mm (max) FBGA package - Pb and Halogen Free Overview The EM68C08C is a high-speed CMOS Double-Data- Rate-Two (DDR2), synchronous dynamic random access memory (SDRAM) containing 1024 Mbits in an 8-bit wide data I/Os. It is internally configured as an 8-bank DRAM, 8 banks x 16Mb addresses x 8 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, Write latency = Read latency -1, Off-Chip Driver (OCD) impedance adjustment and On Die Termination(ODT). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in RAS #, CAS# multiplexing style. Accesses begin with the registration of a Bank Activate command, and then it is followed by a Read or Write command. Read and write accesses to the DDR2 SDRAM are 4 or 8-bit burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Operating the eight memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. A sequential and gapless data rate is possible depending on burst length, CAS latency, and speed grade of the device. Table 1. Ordering Information Part Number Clock Frequency Data Rate EM68C08CWAG-18H 533 MHz 1066Mbps/pin EM68C08CWAG-25H 400 MHz 800Mbps/pin EM68C08CWAG-3H 333 MHz 667Mbps/pin WA: indicates 8 x 10 x 1.2mm FBGA package G: indicates Generation Code H: indicates Pb and Halogen Free Power Supply VDD 1.8V, VDDQ 1.8V VDD 1.8V, VDDQ 1.8V VDD 1.8V, VDDQ 1.8V Package FBGA FBGA FBGA Etron Technology, Inc. No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc. reserves the right to change products or specification without notice. 1 page EtronTech EM68C08CWAG Ball Descriptions Table 3. Ball Details Symbol Type Description CK, CK# Input Differential Clock: CK, CK# are driven by the system clock. All SDRAM input signals are sampled on the crossing of positive edge of CK and negative edge of CK#. Output (Read) data is referenced to the crossings of CK and CK# (both directions of crossing). CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes LOW synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains LOW. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. BA0-BA2 Input Bank Address: BA0-BA2 define to which bank the BankActivate, Read, Write, or Bank Precharge command is being applied. A0-A13 Input Address Inputs: A0-A13 are sampled during the BankActivate command (row address A0-A13) and Read/Write command (column address A0-A9 with A10 defining Auto Precharge). A13 Row Address use on x8 components only. CS# Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code. RAS# Input Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the crossing of positive edges of CK and negative edge of CK#. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH" either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH" the BankActivate command is selected and the bank designated by BA is turned on to the active state. When the WE# is asserted "LOW" the Precharge command is selected and the bank designated by BA is switched to the idle state after the precharge operation. CAS# Input Column Address Strobe: The CAS# signal defines the operation commands in conjunction with the RAS# and WE# signals and is latched at the crossing of positive edges of CK and negative edge of CK#. When RAS# is held "HIGH" and CS# is asserted "LOW" the column access is started by asserting CAS# "LOW". Then, the Read or Write command is selected by asserting WE# "HIGH" or "LOW". WE# Input Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the crossing of positive edges of CK and negative edge of CK#. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. DQS, DQS# RDQS RDQS# Input / Output Bidirectional Data Strobe: output with read data, input with write data. Edge aligned with read data, centered with write data. For the RDQS option using DM pin can be enabled via the EMR(1) to simplify read timing.The data strobes DQS and RDQS may be used in single ended mode or paired with the optional complementary signals DQS# and RDQS# to provide differential pair signaling to the system during both reads and writes. An EMRS (1) control bit enables or disables the complementary data strobe signals. DM DQ0 – DQ7 Input Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle. x8 device, the function of DM or RDQS/RQDS# is enabled by EMRS command. Input / Data I/O: Bi-directional data bus. Output ODT Input On Die Termination: ODT enables internal termination resistance. It is applied to each DQ, DQS/DQS#, RDQS/RDQS# and DM signal. The ODT pin is ignored if the EMR (1) is programmed to disable ODT. VDD Supply Power Supply: +1.8V 0.1V Rev. 1.1 5 Apr. /2016 5 Page EtronTech EM68C08CWAG Table 6-2. Extended Mode Register EMR (1) Bitmap A11 A10 (RDQS Enable) (DQS# Enable) RDQS /DM RDQS# 0(Disable) 0(Disable) 1(Enable) 1(Enable) 0(Enable) 1(Disable) 0(Enable) 1(Disable) DM DM RDQS RDQS Hi-z Hi-z RDQS# Hi-z DQS DQS DQS DQS DQS DQS# DQS# Hi-z DQS# Hi-z EMR(2) The extended mode register (2) controls refresh related features. The default value of the extended mode register (2) is not defined, therefore the extended mode register (2) must be written after power-up for proper operation. The extended mode register(2) is written by asserting LOW on CS#, RAS#, CAS#, WE#, HIGH on BA1 and LOW on BA0, while controlling the states of address pins A0 ~ A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register (2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. Table 7. Extended Mode Register EMR (2) Bitmap BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field 01 1 0 01 SRF 01 DCC PASR3 Extended Mode Register(2) A7 High Temperature Self-Refresh Rate Enable 0 Disable 1 Enable 2 BA1 BA0 MRS mode A3 DCC Enable (Optional) 4 00 MR 0 Disable 0 1 EMR(1) 1 Enable 1 0 EMR(2) 1 1 EMR(3) A2 A1 A0 Partial Array Self Refresh for 8 Banks (Optional) 0 0 0 Full array 0 0 1 Half Array (BA[2:0]=000,001,010&011) 0 1 0 Quarter Array (BA[2:0]= 000&001) 0 1 1 1/8 array (BA[2:0]=000) 1 0 0 3/4 array (BA[2:0]=010,011,100,101,110&111) 1 0 1 Half array (BA[2:0]= 100,101,110&111) 1 1 0 Quarter array (BA[2:0]= 110&111) 1 1 1 1/8 array (BA[2:0]=111) NOTE 1: BA2 and A4-A6, A8-A13 is reserved for future use and must be set to 0 when programming the EMR(2). NOTE 2: Due to the migration nature, user needs to ensure the DRAM part supports higher than 85°C Tcase temperature self-refresh entry. If the high temperature self-refresh mode is supported then controller can set the EMRS2[A7] bit to enable the self-refresh rate in case of higher than 85°C temperature self-refresh operation. NOTE 3: If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued. NOTE 4: DCC (Duty Cycle Corrector) implemented, user may be given the controllability of DCC thru EMR (2) [A3] bit. Rev. 1.1 11 Apr. /2016 11 Page

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