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EM68A16CBQC Schematic ( PDF Datasheet ) - Etron Technology

Teilenummer EM68A16CBQC
Beschreibung 16M x 16 bit DDRII Synchronous DRAM
Hersteller Etron Technology
Logo Etron Technology Logo 




Gesamt 30 Seiten
EM68A16CBQC Datasheet, Funktion
EtronTech
EM68A16CBQC
16M x 16 bit DDRII Synchronous DRAM (SDRAM)
Advance (Rev. 1.1, Jan. /2016)
Features
JEDEC Standard Compliant
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Power supplies: VDD & VDDQ = +1.8V ± 0.1V
Operating temperature: TC = 0 ~ 85 °C
Supports JEDEC clock jitter specification
Fully synchronous operation
Fast clock rate: 333/400/533 MHz
Differential Clock, CK & CK#
Bidirectional single/differential data strobe
- DQS & DQS#
4 internal banks for concurrent operation
4-bit prefetch architecture
Internal pipeline architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5, 6
WRITE latency = READ latency - 1 tCK
Burst length: 4 or 8
Burst type: Sequential / Interleave
DLL enable/disable
Off-Chip Driver (OCD)
- Impedance Adjustment
- Adjustable data-output drive strength
On-die termination (ODT)
RoHS compliant
Auto Refresh and Self Refresh
8192 refresh cycles / 64ms
Package: 84-ball 8 x 12.5 x 1.2mm (max) FBGA
- Pb Free and Halogen Free
Overview
The EM68256WQCA is a high-speed CMOS
Double-Data-Rate-Two (DDR2), synchronous dynamic
random-access memory (SDRAM) containing 256 Mbits
in a 16-bit wide data I/Os. It is internally configured as a
quad bank DRAM, 4 banks x 4Mb addresses x 16 I/Os.
The device is designed to comply with DDR2 DRAM
key features such as posted CAS# with additive latency,
Write latency = Read latency -1, Off-Chip Driver (OCD)
impedance adjustment, and On Die Termination(ODT).
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks
(CK rising and CK# falling) All I/Os are synchronized
with a pair of bidirectional strobes (DQS and DQS#) in
a source synchronous fashion. The address bus is
used to convey row, column, and bank address
information in RAS #, CAS# multiplexing style. Accesses
begin with the registration of a Bank Activate command,
and then it is followed by a Read or Write command.
Read and write accesses to the DDR2 SDRAM are 4
or 8-bit burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Operating the
four memory banks in an interleaved fashion allows
random access operation to occur at a higher rate than
is possible with standard DRAMs. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. A sequential and gapless data rate is
possible depending on burst length, CAS latency, and
speed grade of the device.
Table 1. Ordering Information
Part Number
Clock Frequency Data Rate
EM68A16CBQC-18H
533MHz
1066Mbps/pin
EM68A16CBQC-25H
400MHz
800Mbps/pin
EM68A16CBQC-3H
333MHz
667Mbps/pin
BQ: indicates 8 x 12.5 x 1.2mm FBGA Package
C: indicates Generation Code
H: indicates Pb Free and Halogen Free
Power Supply
VDD 1.8V, VDDQ 1.8V
VDD 1.8V, VDDQ 1.8V
VDD 1.8V, VDDQ 1.8V
Package
FBGA
FBGA
FBGA
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.






EM68A16CBQC Datasheet, Funktion
EtronTech
EM68A16CBQC
VSS
VDDL
VSSDL
VDDQ
VSSQ
VREF
NC
Supply Ground
Supply DLL Power Supply: +1.8V ±0.1V
Supply DLL Ground
Supply DQ Power: +1.8V ±0.1V.
Supply DQ Ground
Supply Reference Voltage for Inputs: +0.5*VDDQ
- No Connect: These pins should be left unconnected.
Rev. 1.1
6
Jan. /2016

6 Page









EM68A16CBQC pdf, datenblatt
EtronTech
EM68A16CBQC
EMR(3)
No function is defined in extended mode register(3).The default value of the extended mode register(3) is not
defined, therefore the extended mode register(3) must be programmed during initialization for proper operation.
Table 8. Extended Mode Register EMR (3) Bitmap
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
11
0*1 Extended Mode Register(3)
NOTE 1: All bits in EMR (3) except BA0 and BA1 are reserved for future use and must be set to 0 when programming the EMR (3).
Rev. 1.1
12
Jan. /2016

12 Page





SeitenGesamt 30 Seiten
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