AD7153 Datasheet PDF - Analog Devices
| Part Number | AD7153 | |
| Description | 12-Bit Capacitance-to-Digital Converter | |
| Manufacturers | Analog Devices | |
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Data Sheet
12-Bit Capacitance-to-Digital Converter
AD7152/AD7153
FEATURES
Capacitance-to-digital converters
Interfaces to floating sensors
Resolution down to 0.25 fF (that is, up to 12 ENOB)
Linearity: 0.05%
Common-mode (not changing) capacitance up to 5 pF
Four capacitance ranges selectable per operation mode
±0.25 pF to ±2 pF in differential mode
0.5 pF to 4 pF in single-ended mode
Tolerant of parasitic capacitance to ground up to 50 pF
Conversion time per channel: 5 ms, 20 ms, 50 ms, and 60 ms
Internal clock oscillator
2-wire serial interface (I2C-compatible)
Power
2.7 V to 3.6 V single-supply operation
100 μA current consumption
Operating temperature: −40°C to +85°C
10-lead MSOP
APPLICATIONS
Automotive, industrial, and medical systems for
Pressure measurement
Position sensing
Level sensing
Flowmeters
Humidity sensing
FUNCTIONAL BLOCK DIAGRAMS
VDD
CIN1(+)
CIN1(–)
EXC1
CIN2(+)
CIN2(–)
EXC2
CAP+
CAP–
AD7152
CLOCK
VOLTAGE
GENERATOR REFERENCE
MUX
12-BIT Σ-∆
MODULATOR
I2C
SERIAL
INTERFACE
SDA
SCL
EXCITATION
DIGITAL
FILTER
CONTROL LOGIC
CALIBRATION
GND
Figure 1.
VDD
CAP+
CAP–
AD7153
CLOCK
VOLTAGE
GENERATOR REFERENCE
CIN1(+)
CIN1(–)
EXC1
MUX
12-BIT Σ-∆
MODULATOR
I2C
SERIAL
INTERFACE
SDA
SCL
EXCITATION
DIGITAL
FILTER
CONTROL LOGIC
CALIBRATION
GND
Figure 2.
GENERAL DESCRIPTION
The AD7152/AD7153 are 12-bit sigma-delta (Σ-Δ) capacitance-to-
digital converters (CDCs). The capacitance to be measured is
connected directly to the device inputs. The architecture features
inherent high resolution (12-bit no missing codes, up to 12-bit
effective resolution) and high linearity (±0.05%). The AD7152/
AD7153 have four capacitance input ranges per operation mode,
±0.25 pF to ±2 pF in differential mode and 0.5 pF to 4 pF in
single-ended mode.
The AD7152/AD7153 can accept up to 5 pF common-mode
capacitance (not changing), which can be balanced by a
programmable on-chip, digital-to-capacitance converter
(CAPDAC).
The AD7153 has one capacitance input channel, while the
AD7152 has two channels. Each channel can be configured
as single-ended or differential. The AD7152/AD7153 are
designed for floating capacitive sensors.
The AD7152/AD7153 have a 2-wire, I2C-compatible serial
interface. Both devices can operate with a single power supply
from 2.7 V to 3.6 V. They are specified over the temperature
range of −40°C to +85°C and are available in a 10-lead MSOP.
Rev. A
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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Data Sheet
AD7152/AD7153
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
SERIAL INTERFACE1, 2
SCL Frequency
SCL High Pulse Width, tHIGH
SCL Low Pulse Width, tLOW
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Hold Time (Start Condition), tHD;STA
Set-Up Time (Start Condition), tSU;STA
Data Set-Up Time, tSU;DAT
Setup Time (Stop Condition), tSU;STO
Data Hold Time, tHD;DAT (Master)
Bus-Free Time (Between Stop and Start Conditions, tBUF)
Min Typ Max Unit Test Conditions/Comments
See Figure 3.
0 400 kHz
0.6 µs
1.3 µs
0.3 µs
0.3 µs
0.6 µs After this period, the first clock is generated.
0.6 µs Relevant for repeated start condition.
0.1 µs
0.6 µs
0.01 µs
1.3 µs
1 Sample tested during initial release to ensure compliance.
2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs;
output load = 10 pF.
SCL
tLOW tR
tHD;STA
tHD;DAT
SDA
tBUF
PS
tF
tHIGH
tSU;DAT
tHD;STA
tSU;STA
S
Figure 3. Serial Interface Timing Diagram
tSU;STO
P
Rev. A | Page 5 of 24
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| Information | Total 24 Pages | |
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