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AD7156 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7156
Beschreibung 2-Channel Capacitance Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 29 Seiten
AD7156 Datasheet, Funktion
Ultralow Power, 1.8 V, 3 mm × 3 mm,
2-Channel Capacitance Converter
AD7156
FEATURES
Ultralow power
Power supply voltage: 1.8 V to 3.6 V
Operation power supply current: 70 μA typical
Power-down current: 2 μA typical
Fast response time
Conversion time: 10 ms per channel
Wake-up time from serial interface: 300 μs
Adaptive environmental compensation
2 capacitance input channels
Sensor capacitance (CSENS): 0 pF up to 13 pF
Sensitivity up to 3 fF
2 modes of operation
Standalone with fixed settings
Interfaced to a microcontroller for user-defined settings
2 detection output flags
2-wire serial interface (I2C-compatible)
Operating temperature: −40°C to +85°C
10-lead LFCSP package (3 mm × 3 mm × 0.8 mm)
APPLICATIONS
Buttons and switches
Proximity sensing
Contactless switching
Position detection
Level detection
Portable products
GENERAL DESCRIPTION
The AD7156 delivers a complete signal processing solution for
capacitive sensors, featuring an ultralow power converter with
fast response time.
The AD7156 uses an Analog Devices, Inc., capacitance-to-
digital converter (CDC) technology, which combines features
important for interfacing to real sensors, such as high input
sensitivity and high tolerance of both input parasitic ground
capacitance and leakage current.
The integrated adaptive threshold algorithm compensates for
any variations in the sensor capacitance due to environmental
factors like humidity and temperature or due to changes in the
dielectric material over time.
By default, the AD7156 operates in standalone mode using the
fixed power-up settings and indicates detection on two digital
outputs. Alternatively, the AD7156 can be interfaced to a micro-
controller via the serial interface, the internal registers can be
programmed with user-defined settings, and the data and status
can be read from the part.
The AD7156 operates with a 1.8 V to 3.6 V power supply. It is
specified over the temperature range of −40°C to +85°C.
CSENS1
CSENS2
CIN1
EXC1
CIN2
EXC2
FUNCTIONAL BLOCK DIAGRAM
VDD
Σ-Δ CDC
MUX AD7156
DIGITAL
FILTER
THRESHOLD
SERIAL
INTERFACE
EXCITATION
THRESHOLD
GND
Figure 1.
SCL
SDA
OUT1
OUT2
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.






AD7156 Datasheet, Funktion
AD7156
TIMING SPECIFICATIONS
VDD = 1.8 V to 3.6 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = VDD, temperature range = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Min Typ Max Unit Test Conditions/Comments
CONVERTER
Conversion Time1
20 ms Both channels, 10 ms per channel.
Wake-Up Time from Power-Down Mode2, 3
0.3 ms
Power-Up Time2, 4
2 ms
Reset Time2, 5
2 ms
SERIAL INTERFACE6, 7
See Figure 2.
SCL Frequency
0 400 kHz
SCL High Pulse Width, tHIGH
0.6 μs
SCL Low Pulse Width, tLOW
1.3 μs
SCL, SDA Rise Time, tR
0.3 μs
SCL, SDA Fall Time, tF
0.3 μs
Hold Time (Start Condition), tHD;STA
0.6 μs After this period, the first clock is generated.
Setup Time (Start Condition), tSU;STA
0.6 μs Relevant for repeated start condition.
Data Setup Time, tSU;DAT
0.1 μs
Setup Time (Stop Condition), tSU;STO
0.6 μs
Data Hold Time (Master), tHD;DAT
10 ns
Bus-Free Time (Between Stop and Start Conditions), tBUF 1.3
μs
1 Conversion time is 304 internal clock cycles for both channels (nominal clock 16 kHz); the internal clock frequency is equal to the specified excitation frequency.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion.
4 Power-up time is the maximum delay between the VDD crossing the minimum level (1.8 V) and either the start of conversion or when ready to receive a serial
interface command.
5 Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial
interface command.
6 Sample tested during initial release to ensure compliance.
7 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
SCL
tLOW tR
tHD;STA
tHD;DAT
SDA
tBUF
PS
tF
tHIGH
tSU;DAT
tHD;STA
tSU;STA
S
Figure 2. Serial Interface Timing Diagram
tSU;STO
P
Rev. 0 | Page 5 of 28

6 Page









AD7156 pdf, datenblatt
AD7156
THEORY OF OPERATION
CIN1
AD7156
CLOCK
GENERATOR
CX1
EXC1
CIN2
MUX
Σ-Δ CDC
CAPDAC
CX2
EXC2
EXCITATION
3.3V
VDD
POWER-DOWN
TIMER
DIGITAL
FILTER
THRESHOLD
THRESHOLD
SERIAL
INTERFACE
SCL
PROGRAMMING
SDA INTERFACE
OUT1
DIGITAL
OUTPUTS
OUT2
GND
Figure 22. AD7156 Block Diagram
The AD7156 core is a high performance capacitance-to-digital
converter (CDC) that allows the part to be interfaced directly
to a capacitive sensor.
The comparators compare the CDC results with thresholds, either
fixed or dynamically adjusted by the on-chip adaptive threshold
algorithm engine. Thus, the outputs indicate a defined change in
the input sensor capacitance.
The AD7156 also integrates an excitation source, CAPDAC
for the capacitive inputs, an input multiplexer, a complete clock
generator, a power-down timer, a power supply monitor, control
logic, and an I2C®-compatible serial interface for configuring the
part and accessing the internal CDC data and status, if required
in the system (see Figure 22).
CAPACITANCE-TO-DIGITAL CONVERTER
Figure 23 shows the CDC simplified functional diagram. The
converter consists of a second-order Σ-Δ charge balancing
modulator and a third-order digital filter. The measured
capacitance CX is connected between an excitation source
and the Σ-Δ modulator input. The excitation signal is applied
on the CX capacitor during the conversion, and the modulator
continuously samples the charge going through the CX. The
digital filter processes the modulator output, which is a stream
of 0s and 1s containing the information in 0 and 1 density. The
data is processed by the adaptive threshold engine and output
comparators; the data can also be read through the serial interface.
The AD7156 is designed for floating capacitive sensors.
Therefore, both CX plates have to be isolated from ground
or any other fixed potential node in the system.
The AD7156 features slew rate limiting on the excitation voltage
output, which decreases the energy of higher harmonics on the
excitation signal and dramatically improves the system electro-
magnetic compatibility (EMC).
CIN
CX
0pF TO 4pF
EXC
CAPACITANCE-TO-DIGITAL CONVERTER
(CDC)
CLOCK
GENERATOR
Σ-Δ
MODULATOR
0x0000 TO 0xFFF0
DATA
DIGITAL
FILTER
EXCITATION
Figure 23. CDC Simplified Block Diagram
CAPDAC
The AD7156 CDC core maximum full-scale input range is 0 pF
to 4 pF. However, the part can accept a higher input capacitance,
caused, for example, by a nonchanging offset capacitance of up to
10 pF. This offset capacitance can be compensated for by using
the programmable on-chip CAPDAC.
CIN
CX
10pF TO 14pF
EXC
CAPDAC
10pF
0x0000 TO 0xFFF0
DATA
0pF TO 4pF
Figure 24. Using a CAPDAC
The CAPDAC can be understood as a negative capacitance
connected internally to a CIN pin. The CAPDAC has a 6-bit
resolution and a monotonic transfer function. Figure 24 shows
how to use the CAPDAC to shift the CDC 0 pF to 4 pF input
range to measure capacitance between 10 pF and 14 pF.
Rev. 0 | Page 11 of 28

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