Datenblatt-pdf.com


8V79S674 Schematic ( PDF Datasheet ) - IDT

Teilenummer 8V79S674
Beschreibung LVPECL Clock Divider and Fanout Buffer
Hersteller IDT
Logo IDT Logo 




Gesamt 21 Seiten
8V79S674 Datasheet, Funktion
Differential-to-3.3V, 2.5V LVPECL
Clock Divider and Fanout Buffer
8V79S674
DATA SHEET
General Description
The 8V79S674 is a clock divider and fanout buffer. The device has
been designed for clock signal division in wireless base station radio
equipment boards. The device is optimized to deliver excellent
additive phase jitter performance. The 8V79S674 uses SiGe
technology for an optimum of high clock frequency and low phase
noise performance, combined with high power supply noise rejection.
The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four
low-skew LVPECL outputs are available and support clock output
frequencies up to 2500MHz (÷1 frequency division). Outputs can be
disabled to save power consumption if not used. The device is
packaged in a lead-free (RoHS 6) 20-lead VFQFN package. The
extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
Features
Clock signal division and distribution
SiGe technology for high-frequency and fast signal rise/fall times
Four low-skew LVPECL clock outputs
Supports frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum frequency: 2500MHz
Maximum output skew: 50ps (maximum)
Maximum LVPECL output rise/fall time: 200ps (maximum)
3.3V or 2.5V core and output supply mode
Supports 1.8V I/O logic levels for all control pins
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
IN ÷N
nIN
2x 50
VT
VREFAC
Reference Voltage
N[1:0]
nOEA
nOEB
Pulldown
Pulldown
Pulldown
.
8V79S674 REVISION 2 04/10/15
Pin Assignment
Q0
nQ0
Q1
nQ1
15 14 13 12 11
VCC 16
10 Q3
Q0 17
9 nQ3
Q2
nQ2
Q3
nQ3
nQ0 18
nOEA 19
VEE 20
1
8V79S674
8 nOEB
7 N1
6 VEE
2 3 45
20-pin, 4mm x 4mm VFQFN Package
1 ©2015 Integrated Device Technology, Inc.






8V79S674 Datasheet, Funktion
8V79S674 DATA SHEET
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C1
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
N=÷1
2500
MHz
fOUT
Output Frequency
N=÷2
N=÷4
1250
625
MHz
MHz
N=÷8
312.5
MHz
fIN
VCMR
Input Frequency
Common Mode
Input Voltage2
IN, nIN
2500
MHz
1.0
VCC – VPP/2
V
VPP
VDIFF_IN
tsk(o)
tsk(pp)
Input Voltage Swing
Differential Input Voltage
Swing
Output Skew3, 4
Part-to-Part Skew3, 5
Noise Floor6
tjit()
Buffer Additive Phase Jitter
100kHz Offset, fOUT = 1228.8MHz
fREF = fOUT = 156.25MHz,
Integration Range: 12kHz to 20MHz
0.15
0.3
22
-146
42
1.3 V
2.6 V
50 ps
200 ps
dBc/Hz
60 fs
Output Isolation
odc Output Duty Cycle
fOUT = 1228.8MHz
fOUT = 614.4MHz
fOUT = 307.2MHz
fOUT = 153.6MHz
50% Input Duty Cycle
90 dBc
90 dBc
90 dBc
95 dBc
44 50 56 %
tR / tF
tPD
Output Rise/Fall Time
Propagation Delay
20% to 80%
200
200 ps
550 ps
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 2. Common mode input voltage is defined as the signal cross point.
NOTE 3. This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 5. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 6. The phase noise at 100kHz offset of the applied input clock is -146 dBc/Hz.
DIFFERENTIAL-TO-3.3V, 2.5V LVPECL
CLOCK DIVIDER AND FANOUT BUFFER
6
REVISION 2 04/10/15

6 Page









8V79S674 pdf, datenblatt
8V79S674 DATA SHEET
Termination for 2.5V LVPECL Outputs
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
level. The R3 in Figure 3B can be eliminated and the termination is
shown in Figure 3C.
VCC = 2.5V
50Ω
50Ω
2.5V LVPECL Driver
2.5V
R1
250Ω
R3
250Ω
2.5V
+
R2
62.5Ω
R4
62.5Ω
VCC = 2.5V
50Ω
50Ω
2.5V LVPECL Driver
2.5V
+
R1 R2
50Ω 50Ω
R3
18Ω
Figure 3A. 2.5V LVPECL Driver Termination Example
Figure 3B. 2.5V LVPECL Driver Termination Example
VCC = 2.5V
50Ω
50Ω
2.5V LVPECL Driver
2.5V
+
R1 R2
50Ω 50Ω
Figure 3C. 2.5V LVPECL Driver Termination Example
DIFFERENTIAL-TO-3.3V, 2.5V LVPECL
CLOCK DIVIDER AND FANOUT BUFFER
12
REVISION 2 04/10/15

12 Page





SeitenGesamt 21 Seiten
PDF Download[ 8V79S674 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
8V79S674LVPECL Clock Divider and Fanout BufferIDT
IDT

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche