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8SLVP2108 Schematic ( PDF Datasheet ) - IDT

Teilenummer 8SLVP2108
Beschreibung LVPECL Output Fanout Buffer
Hersteller IDT
Logo IDT Logo 




Gesamt 22 Seiten
8SLVP2108 Datasheet, Funktion
Low Phase Noise, Dual 1-to-8, 3.3V,
2.5V LVPECL Output Fanout Buffer
8SLVP2108
Datasheet
General Description
The 8SLVP2108 is a high-performance differential dual 1:8
LVPECL fanout buffer. The device is designed for the fanout of
high-frequency, very low additive phase-noise clock and data
signals. The 8SLVP2108 is characterized to operate from a 3.3V or
2.5V power supply. Guaranteed output-to-output and part-to-part
skew characteristics make the 8SLVP2108 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two independent buffers with eight low skew outputs
each are available. The integrated bias voltage references enable
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Block Diagram
PCLKA
nPCLKA
VCC
VREFA
Voltage
Reference
PCLKB
nPCLKB
VCC
VREFB
Voltage
Reference
QA0
nQA0
QA1
nQA1
QA2
nQA2
 
 
 
 
QA7
nQA7
QB0
nQB0
QB1
nQB1
QB2
nQB2
 
 
 
 
QB7
nQB7
Features
Two 1:8, low skew, low additive jitter LVPECL fanout buffers
Two differential clock inputs
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
accept the following differential input levels: LVDS, LVPECL,
CML
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
also accept single-ended LVCMOS levels. See Applications
section Wiring the Differential Input Levels to Accept
Single-ended Levels (Figure 1A and Figure 1B).
Maximum input clock frequency: 2GHz
Output bank skew: 15ps (typical)
Propagation delay: 390ps (maximum)
Low additive phase jitter, RMS: 54fs (maximum)
(fREF = 156.25MHz, VPP = 1V, 12kHz – 20MHz, VCC = 3.3V)
Full 3.3V and 2.5V supply voltage
Maximum device current consumption (IEE): 143mA
Available in Lead-free (RoHS 6), 48-Lead VFQFN package
Supports case temperature 105°C operations
-40°C to 85°C ambient operating temperature
Pin Assignment
VCC
QB3
nQB3
QB4
nQB4
QB5
nQB5
QB6
nQB6
QB7
nQB7
VCC
36 35 34 33 32 31 30 29 28 27 26 25
37 24
38 23
39 22
40 8SLVP2108 21
41 48-lead VFQFN 20
42 7mm x 7mm x 0.8mm 19
43 package body 18
44
45
NL Package
17
16
46 Top View 15
47 14
48 13
1 2 3 4 5 6 7 8 9 10 11 12
VCC
nQA4
QA4
nQA3
QA3
nQA2
QA2
nQA1
QA1
nQA0
QA0
VCC
©2016 Integrated Device Technology, Inc.
1
Revision B, November 21, 2016






8SLVP2108 Datasheet, Funktion
8SLVP2108 Datasheet
Table 4B. Buffer Additive Phase Jitter, tJIT, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
fREF = 122.88MHz Square Wave, VPP = 1V
Integration Range: 1kHz – 40MHz
fREF = 122.88MHz Square Wave, VPP = 1V
Integration Range: 10kHz – 20MHz
fREF = 122.88MHz Square Wave, VPP = 1V
Integration Range: 12kHz – 20MHz
fREF = 156.25MHz Square Wave, VPP = 1V
Integration Range: 1kHz – 40MHz
tJIT
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
fREF = 156.25MHz Square Wave, VPP = 1V
Integration Range: 10kHz – 20MHz
fREF = 156.25MHz Square Wave, VPP = 1V
Integration Range: 12kHz – 20MHz
fREF = 156.25MHz Square Wave, VPP = 0.5V
Integration Range: 1kHz – 40MHz
fREF = 156.25MHz Square Wave, VPP = 0.5V
Integration Range: 10kHz – 20MHz
fREF = 156.25MHz Square Wave, VPP = 0.5V
Integration Range: 12kHz – 20MHz
Typical
97
64
64
62
46
46
50
43
43
Maximum
128
81
81
75
54
54
81
51
51
Units
fs
fs
fs
fs
fs
fs
fs
fs
fs
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
Table 4C. Buffer Additive Phase Jitter, tJIT, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
fREF = 122.88MHz Square Wave, VPP = 1V
Integration Range: 1kHz – 40MHz
fREF = 122.88MHz Square Wave, VPP = 1V
Integration Range: 10kHz – 20MHz
fREF = 122.88MHz Square Wave, VPP = 1V
Integration Range: 12kHz – 20MHz
fREF = 156.25MHz Square Wave, VPP = 1V
Integration Range: 1kHz – 40MHz
tJIT
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
fREF = 156.25MHz Square Wave, VPP = 1V
Integration Range: 10kHz – 20MHz
fREF = 156.25MHz Square Wave, VPP = 1V
Integration Range: 12kHz – 20MHz
fREF = 156.25MHz Square Wave, VPP = 0.5V
Integration Range: 1kHz – 40MHz
fREF = 156.25MHz Square Wave, VPP = 0.5V
Integration Range: 10kHz – 20MHz
fREF = 156.25MHz Square Wave, VPP = 0.5V
Integration Range: 12kHz – 20MHz
Typical
100
68
68
65
48
48
53
45
45
Maximum
132
86
86
77
57
57
81
56
56
Units
fs
fs
fs
fs
fs
fs
fs
fs
fs
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
©2016 Integrated Device Technology, Inc.
6
Revision B, November 21, 2016

6 Page









8SLVP2108 pdf, datenblatt
8SLVP2108 Datasheet
2.5V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS and other differential
signals. Both differential signals must meet the VPP and VCMR input
requirements. Figures 3A to 3C show interface examples for the
PCLK/ nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
2.5V
LVPECL
2.5V
2.5V
PCLK
nPCLK
LVPECL
Input
Figure 3A. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver
Figure 3B. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver with AC Couple
PCLK
nPCLK
Figure 3C. PCLK/nPCLK Input Driven by a
2.5V LVDS Driver
©2016 Integrated Device Technology, Inc.
12
Revision B, November 21, 2016

12 Page





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