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8SLVP1204 Schematic ( PDF Datasheet ) - IDT

Teilenummer 8SLVP1204
Beschreibung LVPECL Output Fanout Buffer
Hersteller IDT
Logo IDT Logo 




Gesamt 25 Seiten
8SLVP1204 Datasheet, Funktion
Low Phase Noise, 2:4, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP1204
DATA SHEET
General Description
The 8SLVP1204 is a high-performance differential LVPECL fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVP1204 is
characterized to operate from a 3.3V or 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVP1204 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and four low skew outputs are available.
The integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
Four low skew, low additive jitter LVPECL output pairs
Two selectable, differential clock input pairs
Differential PCLKx pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Differential PCLKx pairs can also accept single-ended LVCMOS
levels. See Section, “Applications Information”, section, “Wiring
the Differential Input to Accept Single-Ended Levels” (Figures 1A
and 1B)
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input, (input select)
Output skew: 5ps (typical), at 3.63V
Propagation delay: 200ps (typical), at 3.63V
Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
12kHz - 20MHz: 40fs (maximum), at 3.63V
Maximum device current consumption (IEE): 60mA (maximum),
at 3.63V
Full 3.3V±5%, 3.3V±10% or 2.5V±5% supply
Lead-free (RoHS 6), 16-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Supports case temperature 105°C operations
Block Diagram
VCC
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
VCC
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
0 fREF
1
SEL Pulldown
VREF
Voltage
Reference
Pin Assignment
16 15 14 13
Q0
VEE 1
12 nQ1
nQ0
SEL 2
11 Q1
Q1
PCLK1 3
10 nQ0
nQ1 nPCLK1 4
9 Q0
5 6 78
Q2
nQ2
Q3
nQ3 8SLVP1204
16-Lead, 3mm x 3mm VFQFN Package
8SLVP1204 REVISION D 6/8/15
1 ©2015 Integrated Device Technology, Inc.






8SLVP1204 Datasheet, Funktion
8SLVP1204 DATA SHEET
AC Electrical Characteristics
Table 5A. AC Electrical Characteristics, VCC = 3.3V ± 5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C1
Symbol
Parameter
Test Conditions
Minimum
Typical
fREF
Input
PCLK[0:1],
Frequency nPCLK[0:1]
V/t
Input
PCLK[0:1],
Edge Rate nPCLK[0:1]
1.5
tPD
tsk(o)
tsk(i)
Propagation Delay2
Output Skew3 4
Input Skew4
PCKx, nPCLKx to any Qx, nQx
for VPP = 0.1V or 0.3V
120 200
5
5
tsk(p)
tsk(pp)
Pulse Skew
Part-to-Part Skew4 5
fREF = 100MHz
5
100
fREF = 122.88MHz Sine Wave, VPP = 1V,
Integration Range: 1kHz – 40MHz
170
fREF = 122.88MHz Sine Wave, VPP = 1V,
Integration Range: 10kHz – 20MHz
114
fREF = 122.88MHz Sine Wave, VPP = 1V,
Integration Range: 12kHz – 20MHz
114
fREF = 156.25MHz Square Wave,
VPP = 1V, Integration Range:
1kHz – 40MHz
42
fREF = 156.25MHz Square Wave,
Buffer Additive Phase
VPP = 1V, Integration Range:
tJIT
Jitter, RMS; refer to
Additive Phase Jitter
Section
10kHz – 20MHz
fREF = 156.25MHz Square Wave,
VPP = 1V, Integration Range:
12kHz – 20MHz
32
32
fREF = 156.25MHz Square Wave,
VPP = 0.5V, Integration Range:
1kHz – 40MHz
51
fREF = 156.25MHz Square Wave,
VPP = 0.5V, Integration Range:
10kHz – 20MHz
38
fREF = 156.25MHz Square Wave,
VPP = 0.5V, Integration Range:
12kHz – 20MHz
38
tR / tF
MUXISOLATION
VPP
Output Rise/ Fall Time
Mux Isolation6
Peak-to-Peak Input
Voltage7
VCMR
Common Mode Input
Voltage7 8 9
VO(pp)
VDIFF_OUT
Output Voltage Swing,
Peak-to-Peak
Differential Output
Voltage Swing,
Peak-to-Peak
20% to 80%
fREF = 100MHz
fREF < 1.5 GHz
fREF > 1.5 GHz
VPP = > 247mV
VCC = 3.3V, fREF 2GHz
VCC = 2.5V, fREF 2GHz
VCC = 3.3V, fREF 2GHz
VCC = 2.5V, fREF 2GHz
35 90
77
0.1
0.2
1.0
0.8
0.45 0.75
0.4 0.65
0.9 1.5
0.8 1.3
Maximum
2
Units
GHz
V/ns
320 ps
25 ps
50 ps
20 ps
200 ps
fs
fs
fs
51 fs
40 fs
40 fs
71 fs
52 fs
52
180
1.5
1.5
VCC – 0.6
VCC – 0.6
1.0
1.0
2.0
2.0
fs
ps
dB
V
V
V
V
V
V
V
V
LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
6
REVISION D 6/8/15

6 Page









8SLVP1204 pdf, datenblatt
8SLVP1204 DATA SHEET
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
The 8SLVP1204 inputs can be interfaced to LVPECL, LVDS, CML or
LVCMOS drivers. Figure 1A illustrates how to DC couple a single
LVCMOS input to the 8SLVP1204. The value of the series resistance
RS is calculated as the difference between the transmission line
impedance and the driver output impedance. This resistor should be
placed close to the LVCMOS driver. To avoid cross-coupling of
single-ended LVCMOS signals, apply the LVCMOS signals to no
more than one PCLK input.
A practical method to implement Vth is shown in Figure 1B below.
The reference voltage Vth = V1 = VCC/2, is generated by the bias
resistors R1 and R2. The bypass capacitor (C1) is used to help filter
noise on the DC bias. This bias circuit should be located as close to
the input pin as possible.
The ratio of R1 and R2 might need to be adjusted to position the V1
in the center of the input voltage swing. For example, if the input clock
swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted
to set V1 at 1.25V. The values below apply when both the
single-ended swing and VCC are at the same voltage.
VIH
Vth
VIL
LVCMOS
RS
Vth =
VIH + VIL
2
Figure 1A. DC-Coupling a Single LVCMOS Input to the
8SLVP1204
When using single-ended signaling, the noise rejection benefits of
differential signaling are reduced. Even though the differential input
can handle full rail LVCMOS signaling, it is recommended that the
amplitude be reduced, particularly if both input references are
LVCMOS to minimize cross talk. The datasheet specifies a lower
differential amplitude, however this only applies to differential signals.
For single-ended applications, the swing can be larger, however VIL
cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V.
Figure 1B shows a way to attenuate the PCLK input level by a factor
of two as well as matching the transmission line between the
LVCMOS driver and the 8SLVP1204 at both the source and the load.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. R3 and R4 in parallel should equal the transmission
line impedance; for most 50applications, R3 and R4 will be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver.
Though some of the recommended components of Figure 1B might
not be used, the pads should be placed in the layout so that they can
be utilized for debugging purposes. The datasheet specifications are
characterized and guaranteed by using a differential signal.
VCC
Ro
Driver
VCC
R3
100
RS Zo = 50 Ohm
Ro + Rs = Zo
R4
100
C1
0.1uF
VCC
VCC
R1
1K
V1
R2
1K
+
Receiv er
-
Figure 1B. Alternative DC Coupling a Single LVCMOS Input to the 8SLVP1204
LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
12
REVISION D 6/8/15

12 Page





SeitenGesamt 25 Seiten
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